| /freebsd/sys/crypto/des/arch/i386/ |
| H A D | des_enc.S | 85 andl $0xf0f0f0f0, %eax 92 andl $0xfff0000f, %edi 99 andl $0x33333333, %eax 106 andl $0x03fc03fc, %esi 113 andl $0xaaaaaaaa, %eax 120 cmpl $0, %ebx 123 /* Round 0 */ 129 andl $0xfcfcfcfc, %eax 130 andl $0xcfcfcfcf, %edx 137 movl 0x200+_C_LABEL(des_SPtrans)(%ecx),%ebp [all …]
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| /freebsd/sys/crypto/openssl/i386/ |
| H A D | crypt586.S | 52 andl $0xfcfcfcfc,%eax 54 andl $0xcfcfcfcf,%edx 62 xorl 0x200(%ebp,%ecx,1),%edi 65 xorl 0x100(%ebp,%ebx,1),%edi 68 xorl 0x300(%ebp,%ecx,1),%edi 70 andl $0xff,%eax 71 andl $0xff,%edx 72 movl 0x600(%ebp,%ebx,1),%ebx 74 movl 0x700(%ebp,%ecx,1),%ebx 76 movl 0x400(%ebp,%eax,1),%ebx [all …]
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| H A D | des-586.S | 21 andl $0xfcfcfcfc,%eax 22 andl $0xcfcfcfcf,%edx 28 xorl 0x200(%ebp,%ecx,1),%edi 31 xorl 0x100(%ebp,%ebx,1),%edi 34 xorl 0x300(%ebp,%ecx,1),%edi 36 andl $0xff,%eax 37 andl $0xff,%edx 38 xorl 0x600(%ebp,%ebx,1),%edi 39 xorl 0x700(%ebp,%ecx,1),%edi 41 xorl 0x400(%ebp,%eax,1),%edi [all …]
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| /freebsd/sys/contrib/device-tree/include/dt-bindings/clock/ |
| H A D | lpc18xx-ccu.h | 13 #define CLK_APB3_BUS 0x100 14 #define CLK_APB3_I2C1 0x108 15 #define CLK_APB3_DAC 0x110 16 #define CLK_APB3_ADC0 0x118 17 #define CLK_APB3_ADC1 0x120 18 #define CLK_APB3_CAN0 0x128 19 #define CLK_APB1_BUS 0x200 20 #define CLK_APB1_MOTOCON_PWM 0x208 21 #define CLK_APB1_I2C0 0x210 22 #define CLK_APB1_I2S 0x218 [all …]
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| /freebsd/sys/contrib/device-tree/Bindings/phy/ |
| H A D | renesas,usb2-phy.yaml | 56 enum: [0, 1] # and 0 is deprecated. 123 reg = <0xee080200 0x700>; 131 reg = <0xee0a0200 0x700>;
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| H A D | phy-mtk-tphy.txt | 5 controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA. 23 the child's base address to 0, the physical address 72 reg = <0 0x11290000 0 0x800>; 78 reg = <0 0x11290800 0 0x100>; 85 reg = <0 0x11290800 0 0x700>; 92 reg = <0 0x11291000 0 0x100>; 113 phy-names = "usb2-0", "usb3-0"; 122 shared 0x0000 SPLLC 123 0x0100 FMREG 124 u2 port0 0x0800 U2PHY_COM [all …]
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| /freebsd/sys/netinet/ |
| H A D | tcp_syncache.h | 85 #define SCF_NOOPT 0x01 /* no TCP options */ 86 #define SCF_WINSCALE 0x02 /* negotiated window scaling */ 87 #define SCF_TIMESTAMP 0x04 /* negotiated timestamps */ 89 #define SCF_UNREACH 0x10 /* icmp unreachable received */ 90 #define SCF_SIGNATURE 0x20 /* send MD5 digests */ 91 #define SCF_SACK 0x80 /* send SACK option */ 92 #define SCF_ECN_MASK 0x700 /* ECN codepoint mask */ 93 #define SCF_ECN 0x100 /* send ECN setup packet */ 94 #define SCF_ACE_N 0x400 /* send ACE non-ECT setup */ 95 #define SCF_ACE_0 0x500 /* send ACE ECT0 setup */ [all …]
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| /freebsd/sys/contrib/alpine-hal/ |
| H A D | al_hal_pcie_regs.h | 54 #define AL_PCIE_AXI_REGS_OFFSET 0x0 55 #define AL_PCIE_REV_1_2_APP_REGS_OFFSET 0x1000 56 #define AL_PCIE_REV_3_APP_REGS_OFFSET 0x2000 57 #define AL_PCIE_REV_1_2_CORE_CONF_BASE_OFFSET 0x2000 58 #define AL_PCIE_REV_3_CORE_CONF_BASE_OFFSET 0x10000 80 uint32_t rsrvd[(0x270 - 0x224) >> 2]; 85 uint32_t reserved1[(0x10 - 0x4) >> 2]; 87 uint32_t reserved2[(0x18 - 0x14) >> 2]; 90 uint32_t reserved3[(0x48 - 0x20) >> 2]; 94 uint32_t reserved4[(0x10C - 0x54) >> 2]; [all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchExpandAtomicPseudoInsts.cpp | 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 63 char LoongArchExpandAtomicPseudo::ID = 0; 152 Register DestReg = MI.getOperand(0).getReg(); in doAtomicBinOpExpansion() 165 .addImm(0); in doAtomicBinOpExpansion() 212 .addImm(0); in doAtomicBinOpExpansion() 243 Register DestReg = MI.getOperand(0).getReg(); 259 .addImm(0); in doMaskedAtomicBinOpExpansion() 266 .addImm(0); in doMaskedAtomicBinOpExpansion() 294 .addImm(0); in doMaskedAtomicBinOpExpansion() 381 Register DestReg = MI.getOperand(0) in expandAtomicMinMaxOp() [all...] |
| /freebsd/sys/contrib/device-tree/Bindings/soc/fsl/cpm_qe/ |
| H A D | fsl,qe-si.yaml | 39 reg = <0x700 0x80>;
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| H A D | fsl,qe.yaml | 106 reg = <0xe0100000 0x480>; 107 ranges = <0 0xe0100000 0x00100000>; 110 brg-frequency = <0>; 111 bus-frequency = <0x179a7b00>; 113 0x04 0x05 0x0c 0x0d 0x14 0x15 0x1c 0x1d 114 0x24 0x25 0x2c 0x2d 0x34 0x35 0x88 0x89 115 0x98 0x99 0xa8 0xa9 0xb8 0xb9 0xc8 0xc9 116 0xd8 0xd9 0xe8 0xe9>; 120 reg = <0x80 0x80>; 123 interrupts = <95 2 0 0 94 2 0 0>; [all …]
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| /freebsd/sys/contrib/device-tree/src/arm/mediatek/ |
| H A D | mt7629.dtsi | 24 #size-cells = <0>; 27 cpu0: cpu@0 { 30 reg = <0x0>; 38 reg = <0x1>; 51 clk20m: oscillator-0 { 53 #clock-cells = <0>; 60 #clock-cells = <0>; 83 reg = <0x10000000 0x1000>; 89 reg = <0x10002000 0x1000>; 97 reg = <0x10006000 0x1000>; [all …]
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| /freebsd/sys/contrib/device-tree/Bindings/display/msm/ |
| H A D | edp.txt | 34 reg = <0xfd923400 0x700>, 35 <0xfd923a00 0xd4>; 37 interrupts = <12 0>; 54 panel-en-gpios = <&tlmm 137 0>; 55 panel-hpd-gpios = <&tlmm 103 0>;
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| /freebsd/stand/i386/gptboot/ |
| H A D | Makefile | 8 BOOT_COMCONSOLE_PORT?= 0x3f8 10 B2SIOFMT?= 0x3 12 REL1= 0x700 13 ORG1= 0x7c00 14 ORG2= 0x0
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| /freebsd/stand/i386/isoboot/ |
| H A D | Makefile | 9 BOOT_COMCONSOLE_PORT?= 0x3f8 11 B2SIOFMT?= 0x3 13 REL1= 0x700 14 ORG1= 0x7c00 15 ORG2= 0x0 44 echo "$$x bytes available"; test $$x -ge 0
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| /freebsd/stand/i386/gptzfsboot/ |
| H A D | Makefile | 10 BOOT_COMCONSOLE_PORT?= 0x3f8 12 B2SIOFMT?= 0x3 14 REL1= 0x700 15 ORG1= 0x7c00 16 ORG2= 0x0
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| /freebsd/sys/contrib/device-tree/src/arm64/mediatek/ |
| H A D | mt7986a.dtsi | 21 #size-cells = <0>; 22 cpu0: cpu@0 { 24 reg = <0x0>; 32 reg = <0x1>; 40 reg = <0x2>; 48 reg = <0x3>; 58 #clock-cells = <0>; 73 reg = <0 0x43000000 0 0x30000>; 79 reg = <0 0x4fc00000 0 0x00100000>; 83 reg = <0 0x4fd00000 0 0x40000>; [all …]
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| H A D | mt8188.dtsi | 27 #size-cells = <0>; 29 cpu0: cpu@0 { 32 reg = <0x000>; 50 reg = <0x100>; 68 reg = <0x200>; 86 reg = <0x300>; 104 reg = <0x400>; 122 reg = <0x500>; 140 reg = <0x600>; 158 reg = <0x700>; [all …]
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| H A D | mt2712e.dtsi | 22 cluster0_opp: opp-table-0 { 66 #size-cells = <0>; 85 cpu0: cpu@0 { 88 reg = <0x000>; 100 reg = <0x001>; 113 reg = <0x200>; 126 CPU_SLEEP_0: cpu-sleep-0 { 132 arm,psci-suspend-param = <0x0010000>; 135 CLUSTER_SLEEP_0: cluster-sleep-0 { 141 arm,psci-suspend-param = <0x1010000>; [all …]
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| /freebsd/sys/crypto/des/ |
| H A D | des_locl.h | 76 l1=l2=0; \ 89 #define l2c(l,c) (*((c)++)=(unsigned char)(((l) )&0xff), \ 90 *((c)++)=(unsigned char)(((l)>> 8L)&0xff), \ 91 *((c)++)=(unsigned char)(((l)>>16L)&0xff), \ 92 *((c)++)=(unsigned char)(((l)>>24L)&0xff)) 103 #define l2n(l,c) (*((c)++)=(unsigned char)(((l)>>24L)&0xff), \ 104 *((c)++)=(unsigned char)(((l)>>16L)&0xff), \ 105 *((c)++)=(unsigned char)(((l)>> 8L)&0xff), \ 106 *((c)++)=(unsigned char)(((l) )&0xff)) 112 case 8: *(--(c))=(unsigned char)(((l2)>>24L)&0xff); \ [all …]
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| /freebsd/sys/dev/hwpmc/ |
| H A D | hwpmc_uncore.h | 39 #define UCF_EN 0x1 40 #define UCF_PMI 0x4 49 #define UCP_EVSEL(C) ((C) & 0xFF) 50 #define UCP_UMASK(C) ((C) & 0xFF00) 56 #define UCP_CMASK(C) (((C) & 0xFF) << 24) 65 #define UCF_MASK 0xF 67 #define UCF_CTR0 0x394 71 #define UCF_CTRL 0x395 77 #define UCP_PMC0 0x3B0 78 #define UCP_EVSEL0 0x3C0 [all …]
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| /freebsd/stand/i386/boot2/ |
| H A D | Makefile | 5 # A value of 0x80 enables LBA support. 6 BOOT_BOOT1_FLAGS?= 0x80 8 BOOT_COMCONSOLE_PORT?= 0x3f8 10 B2SIOFMT?= 0x3 12 REL1= 0x700 13 ORG1= 0x7c00 14 ORG2= 0x2000 63 echo "$$x bytes available"; test $$x -ge 0 87 ${NM} -t d ${.ALLSRC} | awk '/([0-9])+ T xread/ \
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| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | xlnx,zynq-pinctrl.txt | 43 Valid arguments for 'slew-rate' are '0' and '1' to select between slow and fast 49 spi0_X_ssY (X=0..2, Y=0..2), spi1_0_grp - spi1_3_grp, 50 spi1_X_ssY (X=0..3, Y=0..2), sdio0_0_grp - sdio0_2_grp, 80 reg = <0x700 0x200>; 91 slew-rate = <0>;
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| /freebsd/sys/contrib/device-tree/src/c6x/ |
| H A D | tms320c6472.dtsi | 9 #size-cells = <0>; 11 cpu@0 { 13 reg = <0>; 60 reg = <0x1800000 0x1000>; 66 reg = <0x01840000 0x8400>; 71 ti,core-mask = < 0x01 >; 72 reg = <0x25e0000 0x40>; 77 ti,core-mask = < 0x02 >; 78 reg = <0x25f0000 0x40>; 83 ti,core-mask = < 0x04 >; [all …]
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| /freebsd/sys/contrib/device-tree/Bindings/cpufreq/ |
| H A D | cpufreq-qcom-hw.txt | 40 phandle to a cpufreq_hw followed by the Domain ID(0/1) in the CPU DT node. 51 #size-cells = <0>; 53 CPU0: cpu@0 { 56 reg = <0x0 0x0>; 59 qcom,freq-domain = <&cpufreq_hw 0>; 72 reg = <0x0 0x100>; 75 qcom,freq-domain = <&cpufreq_hw 0>; 85 reg = <0x0 0x200>; 88 qcom,freq-domain = <&cpufreq_hw 0>; 98 reg = <0x0 0x300>; [all …]
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