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/linux/drivers/media/usb/gspca/gl860/
H A Dgl860-ov2640.c12 static u8 c61[] = {0x61}; /* expected */
13 static u8 c51[] = {0x51}; /* expected */
14 static u8 c50[] = {0x50}; /* expected */
15 static u8 c28[] = {0x28}; /* expected */
16 static u8 ca8[] = {0xa8}; /* expected */
27 {0x0000, 0x0000}, {0x0010, 0x0010}, {0x0008, 0x00c0}, {0x0001, 0x00c1},
28 {0x0001, 0x00c2}, {0x0020, 0x0006}, {0x006a, 0x000d},
29 {0x0050, 0x0000}, {0x0041, 0x0000}, {0x006a, 0x0007}, {0x0061, 0x0006},
30 {0x006a, 0x000d}, {0x0000, 0x00c0}, {0x0010, 0x0010}, {0x0001, 0x00c1},
31 {0x0041, 0x00c2}, {0x0004, 0x00d8}, {0x0012, 0x0004}, {0x0000, 0x0058},
[all …]
/linux/drivers/net/ethernet/tehuti/
H A Dtn40_regs.h8 #define TN40_REGS_SIZE 0x10000
10 /* Registers from 0x0000-0x00fc were remapped to 0x4000-0x40fc */
11 #define TN40_REG_TXD_CFG1_0 0x4000
12 #define TN40_REG_TXD_CFG1_1 0x4004
13 #define TN40_REG_TXD_CFG1_2 0x4008
14 #define TN40_REG_TXD_CFG1_3 0x400C
16 #define TN40_REG_RXF_CFG1_0 0x4010
17 #define TN40_REG_RXF_CFG1_1 0x4014
18 #define TN40_REG_RXF_CFG1_2 0x4018
19 #define TN40_REG_RXF_CFG1_3 0x401C
[all …]
H A Dtehuti.h81 # define L32_64(x) (u32) ((u64)(x) & 0xffffffff)
83 # define H32_64(x) 0
105 # define NETDEV_TX_OK 0
134 #define GET_INT_COAL(x) GET_BITS_SHIFT(x, 15, 0)
189 * if len == 0 addr is dma
190 * if len != 0 addr is skb */
207 u64 InUCast; /* 0x7200 */
208 u64 InMCast; /* 0x7210 */
209 u64 InBCast; /* 0x7220 */
210 u64 InPkts; /* 0x7230 */
[all …]
/linux/include/drm/intel/
H A Di915_hdcp_interface.h45 HDCP_DDI_INVALID_PORT = 0x0,
68 HDCP_INVALID_TRANSCODER = 0x00,
72 HDCP_TRANSCODER_A = 0x10,
86 * Initialized to 0 on AKE_INIT. Incremented after every successful
194 FW_HDCP_STATUS_SUCCESS = 0x0000,
197 FW_HDCP_STATUS_INTERNAL_ERROR = 0x1000,
198 FW_HDCP_STATUS_UNKNOWN_ERROR = 0x1001,
199 FW_HDCP_STATUS_INCORRECT_API_VERSION = 0x1002,
200 FW_HDCP_STATUS_INVALID_FUNCTION = 0x1003,
201 FW_HDCP_STATUS_INVALID_BUFFER_LENGTH = 0x1004,
[all …]
/linux/drivers/clk/qcom/
H A Dcamcc-qcs615.c39 { 500000000, 1250000000, 0 },
43 { 1000000000, 2100000000, 0 },
52 .l = 0x1f,
53 .alpha_hi = 0x40,
58 .config_ctl_val = 0x4001055b,
59 .test_ctl_hi_val = 0x1,
60 .test_ctl_hi_mask = 0x1,
64 .offset = 0x0,
83 .l = 0x2a,
84 .alpha_hi = 0x15,
[all …]
H A Dcamcc-sc7180.c34 { 600000000, 3300000000UL, 0 },
38 { 249600000, 2000000000UL, 0 },
43 .l = 0x1f,
44 .alpha = 0x4000,
45 .config_ctl_val = 0x20485699,
46 .config_ctl_hi_val = 0x00002067,
47 .test_ctl_val = 0x40000000,
48 .user_ctl_hi_val = 0x00004805,
49 .user_ctl_val = 0x00000001,
53 .offset = 0x0,
[all …]
H A Dcamcc-sm6350.c36 { 249600000, 2000000000, 0 },
41 .l = 0x1f,
42 .alpha = 0x4000,
43 .config_ctl_val = 0x20485699,
44 .config_ctl_hi_val = 0x00002067,
45 .test_ctl_val = 0x40000000,
46 .test_ctl_hi_val = 0x00000002,
47 .user_ctl_val = 0x00000101,
48 .user_ctl_hi_val = 0x00004805,
52 .offset = 0x0,
[all …]
H A Dgcc-qcs404.c49 { P_XO, 0 },
68 .offset = 0x21000,
71 .enable_reg = 0x45008,
84 .offset = 0x21000,
88 .enable_reg = 0x45000,
89 .enable_mask = BIT(0),
100 .offset = 0x21000,
104 .enable_reg = 0x45000,
105 .enable_mask = BIT(0),
117 .offset = 0x20000,
[all …]
H A Dcamcc-sm8150.c42 { 600000000, 3300000000, 0 },
46 { 249600000, 2000000000, 0 },
50 .l = 0x3e,
51 .alpha = 0x8000,
52 .config_ctl_val = 0x20485699,
53 .config_ctl_hi_val = 0x00002267,
54 .config_ctl_hi1_val = 0x00000024,
55 .test_ctl_val = 0x00000000,
56 .test_ctl_hi_val = 0x00000000,
57 .test_ctl_hi1_val = 0x00000020,
[all …]
H A Dcamcc-sm7150.c43 { 249600000, 2000000000, 0 },
48 .l = 0x3e,
49 .alpha = 0x8000,
50 .post_div_mask = 0xff << 8,
51 .post_div_val = 0x31 << 8,
52 .test_ctl_val = 0x40000000,
56 .offset = 0x0,
100 .l = 0x23,
101 .alpha = 0x6aaa,
102 .post_div_mask = 0xf << 8,
[all …]
H A Dcamcc-sc8180x.c43 { 600000000, 3300000000, 0 },
47 { 249600000, 2000000000, 0 },
51 .l = 0x3e,
52 .alpha = 0x8000,
53 .config_ctl_val = 0x20485699,
54 .config_ctl_hi_val = 0x00002267,
55 .config_ctl_hi1_val = 0x00000024,
56 .test_ctl_hi1_val = 0x00000020,
57 .user_ctl_val = 0x00003100,
58 .user_ctl_hi_val = 0x00000805,
[all …]
H A Dcamcc-sc8280xp.c48 { 249600000, 1800000000, 0 },
52 { 595200000, 3600000000, 0 },
56 .l = 0x3e,
57 .alpha = 0x8000,
58 .config_ctl_val = 0x20485699,
59 .config_ctl_hi_val = 0x00002261,
60 .config_ctl_hi1_val = 0x2a9a699c,
61 .test_ctl_val = 0x00000000,
62 .test_ctl_hi_val = 0x00000000,
63 .test_ctl_hi1_val = 0x01800000,
[all …]
H A Dgcc-sm8250.c36 .offset = 0x0,
39 .enable_reg = 0x52018,
40 .enable_mask = BIT(0),
53 { 0x1, 2 },
58 .offset = 0x0,
75 .offset = 0x76000,
78 .enable_reg = 0x52018,
92 .offset = 0x1c000,
95 .enable_reg = 0x52018,
109 { P_BI_TCXO, 0 },
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dr500_reg.h32 #define R300_GA_POLY_MODE 0x4288
33 # define R300_FRONT_PTYPE_POINT (0 << 4)
36 # define R300_BACK_PTYPE_POINT (0 << 7)
39 #define R300_GA_ROUND_MODE 0x428c
40 # define R300_GEOMETRY_ROUND_TRUNC (0 << 0)
41 # define R300_GEOMETRY_ROUND_NEAREST (1 << 0)
42 # define R300_COLOR_ROUND_TRUNC (0 << 2)
44 #define R300_GB_MSPOS0 0x4010
45 # define R300_MS_X0_SHIFT 0
53 #define R300_GB_MSPOS1 0x4014
[all …]
H A Dcikd.h27 #define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001
28 #define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003
34 #define DIDT_SQ_CTRL0 0x0
35 # define DIDT_CTRL_EN (1 << 0)
36 #define DIDT_DB_CTRL0 0x20
37 #define DIDT_TD_CTRL0 0x40
38 #define DIDT_TCP_CTRL0 0x60
41 #define DPM_TABLE_475 0x3F768
42 # define SamuBootLevel(x) ((x) << 0)
43 # define SamuBootLevel_MASK 0x000000ff
[all …]
H A Devergreend.h33 #define EVERGREEN_MAX_BACKENDS_MASK 0xFF
35 #define EVERGREEN_MAX_SIMDS_MASK 0xFFFF
37 #define EVERGREEN_MAX_PIPES_MASK 0xFF
38 #define EVERGREEN_MAX_LDS_NUM 0xFFFF
40 #define CYPRESS_GB_ADDR_CONFIG_GOLDEN 0x02011003
41 #define BARTS_GB_ADDR_CONFIG_GOLDEN 0x02011003
42 #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003
43 #define JUNIPER_GB_ADDR_CONFIG_GOLDEN 0x02010002
44 #define REDWOOD_GB_ADDR_CONFIG_GOLDEN 0x02010002
45 #define TURKS_GB_ADDR_CONFIG_GOLDEN 0x02010002
[all …]
/linux/sound/soc/mediatek/mt8192/
H A Dmt8192-dai-adda.c19 UL_IIR_SW = 0,
28 AUDIO_SDM_LEVEL_MUTE = 0,
29 AUDIO_SDM_LEVEL_NORMAL = 0x1d,
35 AUDIO_SDM_2ND = 0,
39 #define SDM_AUTO_RESET_THRESHOLD 0x190000
43 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN3, I_DL1_CH1, 1, 0),
44 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN3, I_DL12_CH1, 1, 0),
45 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN3, I_DL2_CH1, 1, 0),
46 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN3, I_DL3_CH1, 1, 0),
47 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN3_1, I_DL4_CH1, 1, 0),
[all...]
/linux/drivers/pinctrl/tegra/
H A Dpinctrl-tegra194.c1333 .mux_bit = 0, \
1348 …efine drive_soc_gpio33_pt0 DRV_PINGROUP_ENTRY_Y(0x1004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1349 …efine drive_soc_gpio32_ps7 DRV_PINGROUP_ENTRY_Y(0x100c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1350 …efine drive_soc_gpio31_ps6 DRV_PINGROUP_ENTRY_Y(0x1014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1351 …efine drive_soc_gpio30_ps5 DRV_PINGROUP_ENTRY_Y(0x101c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1352 …efine drive_aud_mclk_ps4 DRV_PINGROUP_ENTRY_Y(0x1024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1353 …efine drive_dap1_fs_ps3 DRV_PINGROUP_ENTRY_Y(0x102c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1354 …efine drive_dap1_din_ps2 DRV_PINGROUP_ENTRY_Y(0x1034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1355 …efine drive_dap1_dout_ps1 DRV_PINGROUP_ENTRY_Y(0x103c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1356 …efine drive_dap1_sclk_ps0 DRV_PINGROUP_ENTRY_Y(0x1044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb4/
H A Dt4_hw.c55 * at the time it indicated completion is stored there. Returns 0 if the
67 return 0; in t4_wait_op_done_val()
69 if (--attempts == 0) in t4_wait_op_done_val()
168 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a in t4_hw_pci_read_cfg4()
170 * ENABLE is 0 so a simple register write is easier than a in t4_hw_pci_read_cfg4()
173 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0); in t4_hw_pci_read_cfg4()
248 log->cursor = 0; in t4_record_mbox()
250 for (i = 0; i < size / 8; i++) in t4_record_mbox()
253 entry->cmd[i++] = 0; in t4_record_mbox()
278 * The return value is 0 on success or a negative errno on failure. A
[all …]
/linux/fs/nls/
H A Dnls_cp932.c17 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x00-0x07 */
18 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x08-0x0F */
19 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x10-0x17 */
20 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x18-0x1F */
21 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x20-0x27 */
22 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x28-0x2F */
23 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x30-0x37 */
24 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x38-0x3F */
25 0x3000,0x3001,0x3002,0xFF0C,0xFF0E,0x30FB,0xFF1A,0xFF1B,/* 0x40-0x47 */
26 0xFF1F,0xFF01,0x309B,0x309C,0x00B4,0xFF40,0x00A8,0xFF3E,/* 0x48-0x4F */
[all …]
H A Dnls_cp950.c17 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x00-0x07 */
18 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x08-0x0F */
19 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x10-0x17 */
20 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x18-0x1F */
21 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x20-0x27 */
22 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x28-0x2F */
23 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x30-0x37 */
24 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x38-0x3F */
25 0x3000,0xFF0C,0x3001,0x3002,0xFF0E,0x2027,0xFF1B,0xFF1A,/* 0x40-0x47 */
26 0xFF1F,0xFF01,0xFE30,0x2026,0x2025,0xFE50,0xFE51,0xFE52,/* 0x48-0x4F */
[all …]
H A Dnls_cp936.c17 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x00-0x07 */
18 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x08-0x0F */
19 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x10-0x17 */
20 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x18-0x1F */
21 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x20-0x27 */
22 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x28-0x2F */
23 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x30-0x37 */
24 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x38-0x3F */
25 0x4E02,0x4E04,0x4E05,0x4E06,0x4E0F,0x4E12,0x4E17,0x4E1F,/* 0x40-0x47 */
26 0x4E20,0x4E21,0x4E23,0x4E26,0x4E29,0x4E2E,0x4E2F,0x4E31,/* 0x48-0x4F */
[all …]
H A Dnls_cp949.c17 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x00-0x07 */
18 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x08-0x0F */
19 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x10-0x17 */
20 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x18-0x1F */
21 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x20-0x27 */
22 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x28-0x2F */
23 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x30-0x37 */
24 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x38-0x3F */
25 0x0000,0xAC02,0xAC03,0xAC05,0xAC06,0xAC0B,0xAC0C,0xAC0D,/* 0x40-0x47 */
26 0xAC0E,0xAC0F,0xAC18,0xAC1E,0xAC1F,0xAC21,0xAC22,0xAC23,/* 0x48-0x4F */
[all …]