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/linux/drivers/media/usb/stk1160/
H A Dstk1160-reg.h14 #define STK1160_GCTRL 0x000
17 #define STK1160_RMCTL 0x00c
20 #define STK1160_POSVA 0x010
21 #define STK1160_POSV_L 0x010
22 #define STK1160_POSV_M 0x011
23 #define STK1160_POSV_H 0x012
30 * with bit #7 (0x?? OR 0x80 to activate).
32 #define STK1160_DCTRL 0x100
39 * Bit 0 - Horizontal Decimation Control
40 * 0 Horizontal decimation is disabled.
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt76x2/
H A Dusb_mac.c11 s8 offset = 0; in mt76x2u_mac_fixup_xtal()
16 offset = eep_val & 0x7f; in mt76x2u_mac_fixup_xtal()
17 if ((eep_val & 0xff) == 0xff) in mt76x2u_mac_fixup_xtal()
18 offset = 0; in mt76x2u_mac_fixup_xtal()
19 else if (eep_val & 0x80) in mt76x2u_mac_fixup_xtal()
20 offset = 0 - offset; in mt76x2u_mac_fixup_xtal()
23 if (eep_val == 0x00 || eep_val == 0xff) { in mt76x2u_mac_fixup_xtal()
25 eep_val &= 0xff; in mt76x2u_mac_fixup_xtal()
27 if (eep_val == 0x00 || eep_val == 0xff) in mt76x2u_mac_fixup_xtal()
28 eep_val = 0x14; in mt76x2u_mac_fixup_xtal()
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
H A Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
H A Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
/linux/include/dt-bindings/reset/
H A Dhisi,hi6220-resets.h9 #define PERIPH_RSTDIS0_MMC0 0x000
10 #define PERIPH_RSTDIS0_MMC1 0x001
11 #define PERIPH_RSTDIS0_MMC2 0x002
12 #define PERIPH_RSTDIS0_NANDC 0x003
13 #define PERIPH_RSTDIS0_USBOTG_BUS 0x004
14 #define PERIPH_RSTDIS0_POR_PICOPHY 0x005
15 #define PERIPH_RSTDIS0_USBOTG 0x006
16 #define PERIPH_RSTDIS0_USBOTG_32K 0x007
17 #define PERIPH_RSTDIS1_HIFI 0x100
18 #define PERIPH_RSTDIS1_DIGACODEC 0x105
[all …]
/linux/arch/arm/mach-omap2/
H A Domap4-sar-layout.h14 #define SAR_BANK1_OFFSET 0x0000
15 #define SAR_BANK2_OFFSET 0x1000
16 #define SAR_BANK3_OFFSET 0x2000
17 #define SAR_BANK4_OFFSET 0x3000
20 #define SCU_OFFSET0 0xfe4
21 #define SCU_OFFSET1 0xfe8
22 #define OMAP_TYPE_OFFSET 0xfec
23 #define L2X0_SAVE_OFFSET0 0xff0
24 #define L2X0_SAVE_OFFSET1 0xff4
25 #define L2X0_AUXCTRL_OFFSET 0xff8
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx51-pinfunc.h13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
[all …]
H A Dimx6dl-pinfunc.h13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
/linux/Documentation/devicetree/bindings/iio/adc/
H A Dsprd,sc2720-adc.yaml87 #size-cells = <0>;
90 reg = <0x504>;
92 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
/linux/Documentation/devicetree/bindings/nvmem/
H A Dnvmem.yaml39 when it's driven low (logical '0') to allow writing.
59 reg = <0x00700000 0x100000>;
72 reg = <0x404 0x10>;
76 reg = <0x504 0x11>;
81 reg = <0x6 0x2>;
86 reg = <0xc 0x1>;
/linux/drivers/staging/rtl8723bs/hal/
H A Dodm_reg.h16 #define ODM_BB_RESET 0x002
17 #define ODM_DUMMY 0x4fe
18 #define RF_T_METER_OLD 0x24
19 #define RF_T_METER_NEW 0x42
21 #define ODM_EDCA_VO_PARAM 0x500
22 #define ODM_EDCA_VI_PARAM 0x504
23 #define ODM_EDCA_BE_PARAM 0x508
24 #define ODM_EDCA_BK_PARAM 0x50C
25 #define ODM_TXPAUSE 0x522
28 #define ODM_FPGA_PHY0_PAGE8 0x800
[all …]
H A Dodm_RegDefine11N.h13 #define ODM_REG_RF_MODE_11N 0x00
14 #define ODM_REG_RF_0B_11N 0x0B
15 #define ODM_REG_CHNBW_11N 0x18
16 #define ODM_REG_T_METER_11N 0x24
17 #define ODM_REG_RF_25_11N 0x25
18 #define ODM_REG_RF_26_11N 0x26
19 #define ODM_REG_RF_27_11N 0x27
20 #define ODM_REG_RF_2B_11N 0x2B
21 #define ODM_REG_RF_2C_11N 0x2C
22 #define ODM_REG_RXRF_A3_11N 0x3C
[all …]
/linux/drivers/net/ethernet/intel/fm10k/
H A Dfm10k_pf.h15 FM10K_PF_MSG_ID_TEST = 0x000, /* msg ID reserved */
16 FM10K_PF_MSG_ID_XCAST_MODES = 0x001,
17 FM10K_PF_MSG_ID_UPDATE_MAC_FWD_RULE = 0x002,
18 FM10K_PF_MSG_ID_LPORT_MAP = 0x100,
19 FM10K_PF_MSG_ID_LPORT_CREATE = 0x200,
20 FM10K_PF_MSG_ID_LPORT_DELETE = 0x201,
21 FM10K_PF_MSG_ID_CONFIG = 0x300,
22 FM10K_PF_MSG_ID_UPDATE_PVID = 0x400,
23 FM10K_PF_MSG_ID_CREATE_FLOW_TABLE = 0x501,
24 FM10K_PF_MSG_ID_DELETE_FLOW_TABLE = 0x502,
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dsumod.h30 #define RCU_FW_VERSION 0x30c
32 #define RCU_PWR_GATING_SEQ0 0x408
33 #define RCU_PWR_GATING_SEQ1 0x40c
34 #define RCU_PWR_GATING_CNTL 0x410
35 # define PWR_GATING_EN (1 << 0)
36 # define RSVD_MASK (0x3 << 1)
38 # define PCV_MASK (0x1f << 3)
41 # define PCP_MASK (0xf << 8)
44 # define RPW_MASK (0xf << 16)
47 # define ID_MASK (0xf << 24)
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/
H A Ddm.h11 #define MF_USC_LSC 0
14 #define MAIN_ANT 0
17 #define AUX_ANT_CG_TRX 0
18 #define MAIN_ANT_CGCS_RX 0
22 #define DM_REG_RF_MODE_11N 0x00
23 #define DM_REG_RF_0B_11N 0x0B
24 #define DM_REG_CHNBW_11N 0x18
25 #define DM_REG_T_METER_11N 0x24
26 #define DM_REG_RF_25_11N 0x25
27 #define DM_REG_RF_26_11N 0x26
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/
H A Ddm.h7 #define MAIN_ANT 0
10 #define AUX_ANT_CG_TRX 0
11 #define MAIN_ANT_CGCS_RX 0
15 #define DM_REG_RF_MODE_11N 0x00
16 #define DM_REG_RF_0B_11N 0x0B
17 #define DM_REG_CHNBW_11N 0x18
18 #define DM_REG_T_METER_11N 0x24
19 #define DM_REG_RF_25_11N 0x25
20 #define DM_REG_RF_26_11N 0x26
21 #define DM_REG_RF_27_11N 0x27
[all …]
/linux/drivers/gpu/drm/sti/
H A Dsti_hdmi_tx3g4c28phy.c11 #define HDMI_SRZ_CFG 0x504
12 #define HDMI_SRZ_PLL_CFG 0x510
13 #define HDMI_SRZ_ICNTL 0x518
14 #define HDMI_SRZ_CALCODE_EXT 0x520
16 #define HDMI_SRZ_CFG_EN BIT(0)
32 #define PLL_CFG_EN BIT(0)
37 #define ODF_DIV_1 (0)
56 {0, 20000000, 1, ODF_DIV_8},
65 {0, 250000000, {0x0, 0x0, 0x0, 0x0} },
66 {250000000, 300000000, {0x1110, 0x0, 0x0, 0x0} },
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8723be/
H A Ddm.h7 #define MAIN_ANT 0
10 #define AUX_ANT_CG_TRX 0
11 #define MAIN_ANT_CGCS_RX 0
17 #define DM_REG_RF_MODE_11N 0x00
18 #define DM_REG_RF_0B_11N 0x0B
19 #define DM_REG_CHNBW_11N 0x18
20 #define DM_REG_T_METER_11N 0x24
21 #define DM_REG_RF_25_11N 0x25
22 #define DM_REG_RF_26_11N 0x26
23 #define DM_REG_RF_27_11N 0x27
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Ddm.h7 #define MAIN_ANT 0
10 #define AUX_ANT_CG_TRX 0
11 #define MAIN_ANT_CGCS_RX 0
17 #define DM_REG_RF_MODE_11N 0x00
18 #define DM_REG_RF_0B_11N 0x0B
19 #define DM_REG_CHNBW_11N 0x18
20 #define DM_REG_T_METER_11N 0x24
21 #define DM_REG_RF_25_11N 0x25
22 #define DM_REG_RF_26_11N 0x26
23 #define DM_REG_RF_27_11N 0x27
[all …]
/linux/drivers/mfd/
H A Ddb8500-prcmu-regs.h17 #define PRCM_ACLK_MGT (0x004)
18 #define PRCM_SVAMMCSPCLK_MGT (0x008)
19 #define PRCM_SIAMMDSPCLK_MGT (0x00C)
20 #define PRCM_SGACLK_MGT (0x014)
21 #define PRCM_UARTCLK_MGT (0x018)
22 #define PRCM_MSP02CLK_MGT (0x01C)
23 #define PRCM_I2CCLK_MGT (0x020)
24 #define PRCM_SDMMCCLK_MGT (0x024)
25 #define PRCM_SLIMCLK_MGT (0x028)
26 #define PRCM_PER1CLK_MGT (0x02C)
[all …]
/linux/drivers/phy/socionext/
H A Dphy-uniphier-usb2.c18 #define SG_USBPHY1CTRL 0x500
19 #define SG_USBPHY1CTRL2 0x504
20 #define SG_USBPHY2CTRL 0x508
21 #define SG_USBPHY2CTRL2 0x50c /* LD11 */
22 #define SG_USBPHY12PLL 0x50c /* Pro4 */
23 #define SG_USBPHY3CTRL 0x510
24 #define SG_USBPHY3CTRL2 0x514
25 #define SG_USBPHY4CTRL 0x518 /* Pro4 */
26 #define SG_USBPHY4CTRL2 0x51c /* Pro4 */
27 #define SG_USBPHY34PLL 0x51c /* Pro4 */
[all …]
/linux/drivers/net/ethernet/broadcom/asp2/
H A Dbcmasp_intf_defs.h6 ((((intf)->port) * 0x800) + 0xc000)
7 #define UMC_CMD 0x008
8 #define UMC_CMD_TX_EN BIT(0)
10 #define UMC_CMD_SPEED_SHIFT 0x2
11 #define UMC_CMD_SPEED_MASK 0x3
12 #define UMC_CMD_SPEED_10 0x0
13 #define UMC_CMD_SPEED_100 0x1
14 #define UMC_CMD_SPEED_1000 0x2
15 #define UMC_CMD_SPEED_2500 0x3
33 #define UMC_MAC0 0x0c
[all …]

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