1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 204d11269SChen Feng /** 304d11269SChen Feng * This header provides index for the reset controller 404d11269SChen Feng * based on hi6220 SoC. 504d11269SChen Feng */ 604d11269SChen Feng #ifndef _DT_BINDINGS_RESET_CONTROLLER_HI6220 704d11269SChen Feng #define _DT_BINDINGS_RESET_CONTROLLER_HI6220 804d11269SChen Feng 904d11269SChen Feng #define PERIPH_RSTDIS0_MMC0 0x000 1004d11269SChen Feng #define PERIPH_RSTDIS0_MMC1 0x001 1104d11269SChen Feng #define PERIPH_RSTDIS0_MMC2 0x002 1204d11269SChen Feng #define PERIPH_RSTDIS0_NANDC 0x003 1304d11269SChen Feng #define PERIPH_RSTDIS0_USBOTG_BUS 0x004 1404d11269SChen Feng #define PERIPH_RSTDIS0_POR_PICOPHY 0x005 1504d11269SChen Feng #define PERIPH_RSTDIS0_USBOTG 0x006 1604d11269SChen Feng #define PERIPH_RSTDIS0_USBOTG_32K 0x007 1704d11269SChen Feng #define PERIPH_RSTDIS1_HIFI 0x100 1804d11269SChen Feng #define PERIPH_RSTDIS1_DIGACODEC 0x105 1904d11269SChen Feng #define PERIPH_RSTEN2_IPF 0x200 2004d11269SChen Feng #define PERIPH_RSTEN2_SOCP 0x201 2104d11269SChen Feng #define PERIPH_RSTEN2_DMAC 0x202 2204d11269SChen Feng #define PERIPH_RSTEN2_SECENG 0x203 2304d11269SChen Feng #define PERIPH_RSTEN2_ABB 0x204 2404d11269SChen Feng #define PERIPH_RSTEN2_HPM0 0x205 2504d11269SChen Feng #define PERIPH_RSTEN2_HPM1 0x206 2604d11269SChen Feng #define PERIPH_RSTEN2_HPM2 0x207 2704d11269SChen Feng #define PERIPH_RSTEN2_HPM3 0x208 2804d11269SChen Feng #define PERIPH_RSTEN3_CSSYS 0x300 2904d11269SChen Feng #define PERIPH_RSTEN3_I2C0 0x301 3004d11269SChen Feng #define PERIPH_RSTEN3_I2C1 0x302 3104d11269SChen Feng #define PERIPH_RSTEN3_I2C2 0x303 3204d11269SChen Feng #define PERIPH_RSTEN3_I2C3 0x304 3304d11269SChen Feng #define PERIPH_RSTEN3_UART1 0x305 3404d11269SChen Feng #define PERIPH_RSTEN3_UART2 0x306 3504d11269SChen Feng #define PERIPH_RSTEN3_UART3 0x307 3604d11269SChen Feng #define PERIPH_RSTEN3_UART4 0x308 3704d11269SChen Feng #define PERIPH_RSTEN3_SSP 0x309 3804d11269SChen Feng #define PERIPH_RSTEN3_PWM 0x30a 3904d11269SChen Feng #define PERIPH_RSTEN3_BLPWM 0x30b 4004d11269SChen Feng #define PERIPH_RSTEN3_TSENSOR 0x30c 4104d11269SChen Feng #define PERIPH_RSTEN3_DAPB 0x312 4204d11269SChen Feng #define PERIPH_RSTEN3_HKADC 0x313 4304d11269SChen Feng #define PERIPH_RSTEN3_CODEC_SSI 0x314 4404d11269SChen Feng #define PERIPH_RSTEN3_PMUSSI1 0x316 4504d11269SChen Feng #define PERIPH_RSTEN8_RS0 0x400 4604d11269SChen Feng #define PERIPH_RSTEN8_RS2 0x401 4704d11269SChen Feng #define PERIPH_RSTEN8_RS3 0x402 4804d11269SChen Feng #define PERIPH_RSTEN8_MS0 0x403 4904d11269SChen Feng #define PERIPH_RSTEN8_MS2 0x405 5004d11269SChen Feng #define PERIPH_RSTEN8_XG2RAM0 0x406 5104d11269SChen Feng #define PERIPH_RSTEN8_X2SRAM_TZMA 0x407 5204d11269SChen Feng #define PERIPH_RSTEN8_SRAM 0x408 5304d11269SChen Feng #define PERIPH_RSTEN8_HARQ 0x40a 5404d11269SChen Feng #define PERIPH_RSTEN8_DDRC 0x40c 5504d11269SChen Feng #define PERIPH_RSTEN8_DDRC_APB 0x40d 5604d11269SChen Feng #define PERIPH_RSTEN8_DDRPACK_APB 0x40e 5704d11269SChen Feng #define PERIPH_RSTEN8_DDRT 0x411 5804d11269SChen Feng #define PERIPH_RSDIST9_CARM_DAP 0x500 5904d11269SChen Feng #define PERIPH_RSDIST9_CARM_ATB 0x501 6004d11269SChen Feng #define PERIPH_RSDIST9_CARM_LBUS 0x502 6104d11269SChen Feng #define PERIPH_RSDIST9_CARM_POR 0x503 6204d11269SChen Feng #define PERIPH_RSDIST9_CARM_CORE 0x504 6304d11269SChen Feng #define PERIPH_RSDIST9_CARM_DBG 0x505 6404d11269SChen Feng #define PERIPH_RSDIST9_CARM_L2 0x506 6504d11269SChen Feng #define PERIPH_RSDIST9_CARM_SOCDBG 0x507 6604d11269SChen Feng #define PERIPH_RSDIST9_CARM_ETM 0x508 6704d11269SChen Feng 68339d00cbSXinliang Liu #define MEDIA_G3D 0 69339d00cbSXinliang Liu #define MEDIA_CODEC_VPU 2 70339d00cbSXinliang Liu #define MEDIA_CODEC_JPEG 3 71339d00cbSXinliang Liu #define MEDIA_ISP 4 72339d00cbSXinliang Liu #define MEDIA_ADE 5 73339d00cbSXinliang Liu #define MEDIA_MMU 6 74339d00cbSXinliang Liu #define MEDIA_XG2RAM1 7 75339d00cbSXinliang Liu 76*5f912f7cSPeter Griffin #define AO_G3D 1 77*5f912f7cSPeter Griffin #define AO_CODECISP 2 78*5f912f7cSPeter Griffin #define AO_MCPU 4 79*5f912f7cSPeter Griffin #define AO_BBPHARQMEM 5 80*5f912f7cSPeter Griffin #define AO_HIFI 8 81*5f912f7cSPeter Griffin #define AO_ACPUSCUL2C 12 82*5f912f7cSPeter Griffin 8304d11269SChen Feng #endif /*_DT_BINDINGS_RESET_CONTROLLER_HI6220*/ 84