| /linux/arch/arm/mach-omap2/ |
| H A D | omap54xx.h | 17 #define L4_54XX_BASE 0x4a000000
18 #define L4_WK_54XX_BASE 0x4ae00000
19 #define L4_PER_54XX_BASE 0x48000000
20 #define L3_54XX_BASE 0x44000000
21 #define OMAP54XX_32KSYNCT_BASE 0x4ae04000
22 #define OMAP54XX_CM_CORE_AON_BASE 0x4a004000
23 #define OMAP54XX_CM_CORE_BASE 0x4a008000
24 #define OMAP54XX_PRM_BASE 0x4ae06000
25 #define OMAP54XX_PRCM_MPU_BASE 0x48243000
26 #define OMAP54XX_SCM_BASE 0x4a002000
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| H A D | iomap.h | 33 #define OMAP2_L3_IO_OFFSET 0x90000000
36 #define OMAP2_L4_IO_OFFSET 0xb2000000
39 #define OMAP4_L3_IO_OFFSET 0xb4000000
42 #define AM33XX_L4_WK_IO_OFFSET 0xb5000000
45 #define OMAP4_L3_PER_IO_OFFSET 0xb1100000
48 #define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
58 #define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
61 #define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
65 #define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
70 /* 0x6e000000 --> 0xfe000000 */
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| H A D | am33xx.h | 11 #define L4_SLOW_AM33XX_BASE 0x48000000
13 #define AM33XX_SCM_BASE 0x44E10000
15 #define AM33XX_PRCM_BASE 0x44E00000
16 #define AM43XX_PRCM_BASE 0x44DF0000
17 #define AM33XX_TAP_BASE (AM33XX_CTRL_BASE + 0x3FC)
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| H A D | ti81xx.h | 11 #define L4_SLOW_TI81XX_BASE 0x48000000
13 #define TI81XX_SCM_BASE 0x48140000
15 #define TI81XX_PRCM_BASE 0x48180000
19 * TI81XX register for checking device ID (it adds 0x204 to tap base while
20 * TI81XX DEVICE ID register is at offset 0x600 from control base).
23 TI81XX_CONTROL_DEVICE_ID - 0x204)
26 #define TI81XX_ARM_INTC_BASE 0x48200000
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| H A D | omap44xx.h | 17 #define L4_44XX_BASE 0x4a000000
18 #define L4_WK_44XX_BASE 0x4a300000
19 #define L4_PER_44XX_BASE 0x48000000
20 #define L4_EMU_44XX_BASE 0x54000000
21 #define L3_44XX_BASE 0x44000000
22 #define OMAP44XX_EMIF1_BASE 0x4c000000
23 #define OMAP44XX_EMIF2_BASE 0x4d000000
24 #define OMAP44XX_DMM_BASE 0x4e000000
25 #define OMAP4430_32KSYNCT_BASE 0x4a304000
26 #define OMAP4430_CM1_BASE 0x4a004000
[all …]
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| H A D | omap34xx.h | 17 #define L4_34XX_BASE 0x48000000
18 #define L4_WK_34XX_BASE 0x48300000
19 #define L4_PER_34XX_BASE 0x49000000
20 #define L4_EMU_34XX_BASE 0x54000000
21 #define L3_34XX_BASE 0x68000000
23 #define L4_WK_AM33XX_BASE 0x44C00000
25 #define OMAP3430_32KSYNCT_BASE 0x48320000
26 #define OMAP3430_CM_BASE 0x48004800
27 #define OMAP3430_PRM_BASE 0x48306800
28 #define OMAP343X_SMS_BASE 0x6C000000
[all …]
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| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | intel,ixp4xx-pci.yaml | 54 - const: 0xf800
55 - const: 0
56 - const: 0
73 reg = <0xc0000000 0x1000>;
77 bus-range = <0x00 0xff>;
80 <0x02000000 0 0x48000000 0x48000000 0 0x04000000>,
81 <0x01000000 0 0x00000000 0x4c000000 0 0x00010000>;
83 <0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
86 interrupt-map-mask = <0xf800 0 0 7>;
88 <0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */
[all …]
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| /linux/arch/arm64/boot/dts/ti/ |
| H A D | k3-am64.dtsi | 54 ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
55 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
56 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
57 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
58 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
59 <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
60 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
61 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
62 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x00000100>, /* Main RTI0 */
63 <0x00 0x0e010000 0x00 0x0e010000 0x00 0x00000100>, /* Main RTI1 */
[all …]
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| H A D | k3-am62.dtsi | 77 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
78 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
79 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
80 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
81 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
82 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
83 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
84 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
85 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
86 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
[all …]
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| H A D | k3-am62a.dtsi | 81 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
82 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
83 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
84 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
85 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
86 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
87 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
88 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
89 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
90 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
[all …]
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| /linux/drivers/scsi/ |
| H A D | 53c700_d.h_shipped | 28 ABSOLUTE Device_ID = 0 ; ID of target for command
29 ABSOLUTE MessageCount = 0 ; Number of bytes in message
30 ABSOLUTE MessageLocation = 0 ; Addr of message
31 ABSOLUTE CommandCount = 0 ; Number of bytes in command
32 ABSOLUTE CommandAddress = 0 ; Addr of Command
33 ABSOLUTE StatusAddress = 0 ; Addr to receive status return
34 ABSOLUTE ReceiveMsgAddress = 0 ; Addr to receive msg
42 ABSOLUTE SGScriptStartAddress = 0
45 ; this: 0xPRS where
48 ABSOLUTE AFTER_SELECTION = 0x100
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| /linux/arch/arm64/boot/dts/renesas/ |
| H A D | r8a774a1-hihope-rzg2m.dts | 19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x6 0x00000000 0x0 0x80000000>;
35 clock-names = "du.0", "du.1", "du.2",
36 "dclkin.0", "dclkin.1", "dclkin.2";
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| H A D | r8a774e1-hihope-rzg2h.dts | 19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x5 0x00000000 0x0 0x80000000>;
35 clock-names = "du.0", "du.1", "du.3",
36 "dclkin.0", "dclkin.1", "dclkin.3";
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| H A D | r8a774a1-hihope-rzg2m-rev2.dts | 19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x6 0x00000000 0x0 0x80000000>;
35 clock-names = "du.0", "du.1", "du.2",
36 "dclkin.0", "dclkin.1", "dclkin.2";
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| H A D | r8a779m5-salvator-xs.dts | 23 reg = <0x0 0x48000000 0x0 0x78000000>;
34 clock-names = "du.0", "du.1", "du.3",
35 "dclkin.0", "dclkin.1", "dclkin.3";
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| H A D | r8a774b1-hihope-rzg2n.dts | 19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x4 0x80000000 0x0 0x80000000>;
35 clock-names = "du.0", "du.1", "du.3",
36 "dclkin.0", "dclkin.1", "dclkin.3";
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| H A D | r8a774b1-hihope-rzg2n-rev2.dts | 19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x4 0x80000000 0x0 0x80000000>;
35 clock-names = "du.0", "du.1", "du.3",
36 "dclkin.0", "dclkin.1", "dclkin.3";
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| H A D | r8a779m3-salvator-xs.dts | 23 reg = <0x0 0x48000000 0x0 0x78000000>;
28 reg = <0x4 0x80000000 0x0 0x80000000>;
33 reg = <0x6 0x00000000 0x1 0x00000000>;
44 clock-names = "du.0", "du.1", "du.2",
45 "dclkin.0", "dclkin.1", "dclkin.2";
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| H A D | r8a779m3-ulcb.dts | 22 reg = <0x0 0x48000000 0x0 0x78000000>;
27 reg = <0x4 0x80000000 0x0 0x80000000>;
32 reg = <0x6 0x00000000 0x1 0x00000000>;
43 clock-names = "du.0", "du.1", "du.2",
44 "dclkin.0", "dclkin.1", "dclkin.2";
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| H A D | r8a77951-ulcb.dts | 3 * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board with R-Car H3 ES2.0+
20 reg = <0x0 0x48000000 0x0 0x38000000>;
25 reg = <0x5 0x00000000 0x0 0x40000000>;
30 reg = <0x6 0x00000000 0x0 0x40000000>;
35 reg = <0x7 0x00000000 0x0 0x40000000>;
48 clock-names = "du.0", "du.1", "du.2", "du.3",
49 "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
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| H A D | r8a77951-salvator-x.dts | 3 * Device Tree Source for the Salvator-X board with R-Car H3 ES2.0
19 reg = <0x0 0x48000000 0x0 0x38000000>;
24 reg = <0x5 0x00000000 0x0 0x40000000>;
29 reg = <0x6 0x00000000 0x0 0x40000000>;
34 reg = <0x7 0x00000000 0x0 0x40000000>;
47 clock-names = "du.0", "du.1", "du.2", "du.3",
48 "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
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| H A D | r8a77951-salvator-xs.dts | 3 * Device Tree Source for the Salvator-X 2nd version board with R-Car H3 ES2.0+
19 reg = <0x0 0x48000000 0x0 0x38000000>;
24 reg = <0x5 0x00000000 0x0 0x40000000>;
29 reg = <0x6 0x00000000 0x0 0x40000000>;
34 reg = <0x7 0x00000000 0x0 0x40000000>;
47 clock-names = "du.0", "du.1", "du.2", "du.3",
48 "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
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| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | faraday,ftintc010.yaml | 48 reg = <0x48000000 0x1000>;
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| /linux/arch/arm/mach-pxa/ |
| H A D | addr-map.h | 8 #define PXA_CS0_PHYS 0x00000000
9 #define PXA_CS1_PHYS 0x04000000
10 #define PXA_CS2_PHYS 0x08000000
11 #define PXA_CS3_PHYS 0x0C000000
12 #define PXA_CS4_PHYS 0x10000000
13 #define PXA_CS5_PHYS 0x14000000
15 #define PXA300_CS0_PHYS 0x00000000 /* PXA300/PXA310 _only_ */
16 #define PXA300_CS1_PHYS 0x30000000 /* PXA300/PXA310 _only_ */
17 #define PXA3xx_CS2_PHYS 0x10000000
18 #define PXA3xx_CS3_PHYS 0x14000000
[all …]
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| /linux/Documentation/arch/arm/ |
| H A D | ixp4xx.rst | 78 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB).
87 for up to 128MB (0x48000000 to 0x4fffffff) of memory on the bus.
|