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/freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/
H A Dmsi-pic.txt45 reg = <0x41600 0x80>;
46 msi-available-ranges = <0 0x100>;
48 0xe0 0
49 0xe1 0
50 0xe2 0
51 0xe3 0
52 0xe4 0
53 0xe5 0
54 0xe6 0
55 0xe7 0>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dfsl,mpic-msi.yaml145 reg = <0x41600 0x80>;
146 msi-available-ranges = <0 0x100>;
147 interrupts = <0xe0 0>, <0xe1 0>, <0xe2 0>, <0xe3 0>,
148 <0xe4 0>, <0xe5 0>, <0xe6 0>, <0xe7 0>;
154 reg = <0x41600 0x200>, <0x44148 4>;
155 interrupts = <0xe0 0 0 0>, <0xe1 0 0 0>, <0xe2 0 0 0>, <0xe3 0 0 0>,
156 <0xe4 0 0 0>, <0xe5 0 0 0>, <0xe6 0 0 0>, <0xe7 0 0 0>,
157 <0x100 0 0 0>, <0x101 0 0 0>, <0x102 0 0 0>, <0x103 0 0 0>,
158 <0x104 0 0 0>, <0x105 0 0 0>, <0x106 0 0 0>, <0x107 0 0 0>;
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dpq3-mpic.dtsi2 * PQ3 MPIC device tree stub [ controller @ offset 0x40000 ]
37 #address-cells = <0>;
39 reg = <0x40000 0x40000>;
49 reg = <0x41100 0x100 0x41300 4>;
50 interrupts = <0 0 3 0
51 1 0 3 0
52 2 0 3 0
53 3 0 3 0>;
58 reg = <0x41400 0x200>;
60 0xb0 2 0 0
[all …]
H A Dqoriq-mpic.dtsi2 * QorIQ MPIC device tree stub [ controller @ offset 0x40000 ]
37 #address-cells = <0>;
39 reg = <0x40000 0x40000>;
42 clock-frequency = <0x0>;
47 reg = <0x41100 0x100 0x41300 4>;
48 interrupts = <0 0 3 0
49 1 0 3 0
50 2 0 3 0
51 3 0 3 0>;
56 reg = <0x41600 0x200 0x44140 4>;
[all …]
H A Dqoriq-mpic4.3.dtsi2 * QorIQ MPIC device tree stub [ controller @ offset 0x40000 ]
37 #address-cells = <0>;
39 reg = <0x40000 0x40000>;
42 clock-frequency = <0x0>;
47 reg = <0x41100 0x100 0x41300 4>;
48 interrupts = <0 0 3 0
49 1 0 3 0
50 2 0 3 0
51 3 0 3 0>;
56 reg = <0x41600 0x200 0x44148 4>;
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dmpc8610_hpcd.dts26 #size-cells = <0>;
28 PowerPC,8610@0 {
30 reg = <0>;
35 sleep = <&pmc 0x00008000 0 // core
36 &pmc 0x00004000 0>; // timebase
37 timebase-frequency = <0>; // From uboot
38 bus-frequency = <0>; // From uboot
39 clock-frequency = <0>; // From uboot
45 reg = <0x00000000 0x20000000>; // 512M at 0x0
52 reg = <0xe0005000 0x1000>;
[all …]
H A Dxpedite5301.dts16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
29 #size-cells = <0>;
31 PowerPC,8572@0 {
33 reg = <0x0>;
36 d-cache-size = <0x8000>; // L1, 32K
37 i-cache-size = <0x8000>; // L1, 32K
38 timebase-frequency = <0>;
39 bus-frequency = <0>;
40 clock-frequency = <0>;
46 reg = <0x1>;
[all …]
H A Dxpedite5370.dts27 #size-cells = <0>;
29 PowerPC,8572@0 {
31 reg = <0x0>;
34 d-cache-size = <0x8000>; // L1, 32K
35 i-cache-size = <0x8000>; // L1, 32K
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
44 reg = <0x1>;
47 d-cache-size = <0x8000>; // L1, 32K
[all …]
H A Dxcalibur1501.dts28 #size-cells = <0>;
30 PowerPC,8572@0 {
32 reg = <0x0>;
35 d-cache-size = <0x8000>; // L1, 32K
36 i-cache-size = <0x8000>; // L1, 32K
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
45 reg = <0x1>;
48 d-cache-size = <0x8000>; // L1, 32K
[all …]
H A Dxpedite5330.dts16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
30 #size-cells = <0>;
32 pmcslot@0 {
33 cell-index = <0>;
44 #size-cells = <0>;
46 xmcslot@0 {
47 cell-index = <0>;
65 #size-cells = <0>;
67 PowerPC,8572@0 {
69 reg = <0x0>;
[all …]
/freebsd/sys/dts/powerpc/
H A Dp1020rdb.dts55 #size-cells = <0>;
57 PowerPC,P1020@0 {
59 reg = <0x0>;
65 reg = <0x1>;
78 reg = <0 0xffe05000 0 0x1000>;
83 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
84 0x1 0x0 0x0 0xffa00000 0x00040000
85 0x2 0x0 0x0 0xffb00000 0x00020000>;
87 nor@0,0 {
91 reg = <0x0 0x0 0x1000000>;
[all …]
H A Dp2020ds.dts81 #size-cells = <0>;
83 PowerPC,P2020@0 {
85 reg = <0x0>;
91 reg = <0x1>;
104 reg = <0 0xffe05000 0 0x1000>;
108 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
109 0x1 0x0 0x0 0xe0000000 0x08000000
110 0x2 0x0 0x0 0xffa00000 0x00040000
111 0x3 0x0 0x0 0xffdf0000 0x00008000
112 0x4 0x0 0x0 0xffa40000 0x00040000
[all …]
H A Dmpc8572ds.dts82 #size-cells = <0>;
84 PowerPC,8572@0 {
86 reg = <0x0>;
89 d-cache-size = <0x8000>; // L1, 32K
90 i-cache-size = <0x8000>; // L1, 32K
91 timebase-frequency = <0>;
92 bus-frequency = <0>;
93 clock-frequency = <0>;
99 reg = <0x1>;
102 d-cache-size = <0x8000>; // L1, 32K
[all …]
H A Dp3041si.dtsi103 #size-cells = <0>;
105 cpu0: PowerPC,e500mc@0 {
107 reg = <0>;
145 dcsr-epu@0 {
147 interrupts = <52 2 0 0
148 84 2 0 0
149 85 2 0 0>;
151 reg = <0x0 0x1000>;
155 reg = <0x1000 0x1000 0x1000000 0x8000>;
159 reg = <0x2000 0x1000>;
[all …]
H A Dp2041si.dtsi102 #size-cells = <0>;
104 cpu0: PowerPC,e500mc@0 {
106 reg = <0>;
144 dcsr-epu@0 {
146 interrupts = <52 2 0 0
147 84 2 0 0
148 85 2 0 0>;
150 reg = <0x0 0x1000>;
154 reg = <0x1000 0x1000 0x1000000 0x8000>;
158 reg = <0x2000 0x1000>;
[all …]
H A Dp5020si.dtsi109 #size-cells = <0>;
111 cpu0: PowerPC,e5500@0 {
113 reg = <0>;
135 dcsr-epu@0 {
137 interrupts = <52 2 0 0
138 84 2 0 0
139 85 2 0 0>;
141 reg = <0x0 0x1000>;
145 reg = <0x1000 0x1000 0x1000000 0x8000>;
149 reg = <0x2000 0x1000>;
[all …]