/linux/Documentation/devicetree/bindings/soc/ti/ |
H A D | ti,j721e-system-controller.yaml | 48 "^mux-controller@[0-9a-f]+$": 53 "^clock-controller@[0-9a-f]+$": 59 "phy@[0-9a-f]+$": 65 "^chipid@[0-9a-f]+$": 84 reg = <0x00100000 0x1c000>; 91 reg = <0x00004080 0x50>; 95 <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 96 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ 97 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ 98 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */ [all …]
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/linux/arch/arm64/boot/dts/amlogic/ |
H A D | amlogic-t7.dtsi | 16 #address-cells = <0x2>; 17 #size-cells = <0x0>; 54 reg = <0x0 0x100>; 61 reg = <0x0 0x101>; 68 reg = <0x0 0x102>; 75 reg = <0x0 0x103>; 79 cpu0: cpu@0 { 82 reg = <0x0 0x0>; 89 reg = <0x0 0x1>; 96 reg = <0x0 0x2>; [all …]
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H A D | meson-s4.dtsi | 18 #size-cells = <0>; 20 cpu0: cpu@0 { 23 reg = <0x0 0x0>; 30 reg = <0x0 0x1>; 37 reg = <0x0 0x2>; 44 reg = <0x0 0x3>; 66 #clock-cells = <0>; 89 #address-cells = <0>; 91 reg = <0x0 0xfff01000 0 0x1000>, 92 <0x0 0xfff02000 0 0x2000>, [all …]
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/linux/drivers/net/ethernet/tehuti/ |
H A D | tn40_regs.h | 8 #define TN40_REGS_SIZE 0x10000 10 /* Registers from 0x0000-0x00fc were remapped to 0x4000-0x40fc */ 11 #define TN40_REG_TXD_CFG1_0 0x4000 12 #define TN40_REG_TXD_CFG1_1 0x4004 13 #define TN40_REG_TXD_CFG1_2 0x4008 14 #define TN40_REG_TXD_CFG1_3 0x400C 16 #define TN40_REG_RXF_CFG1_0 0x4010 17 #define TN40_REG_RXF_CFG1_1 0x4014 18 #define TN40_REG_RXF_CFG1_2 0x4018 19 #define TN40_REG_RXF_CFG1_3 0x401C [all …]
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H A D | tehuti.h | 81 # define L32_64(x) (u32) ((u64)(x) & 0xffffffff) 83 # define H32_64(x) 0 105 # define NETDEV_TX_OK 0 134 #define GET_INT_COAL(x) GET_BITS_SHIFT(x, 15, 0) 189 * if len == 0 addr is dma 190 * if len != 0 addr is skb */ 207 u64 InUCast; /* 0x7200 */ 208 u64 InMCast; /* 0x7210 */ 209 u64 InBCast; /* 0x7220 */ 210 u64 InPkts; /* 0x7230 */ [all …]
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/linux/arch/arm/boot/dts/nxp/mxs/ |
H A D | imx28-pinfunc.h | 13 #define MX28_PAD_GPMI_D00__GPMI_D0 0x0000 14 #define MX28_PAD_GPMI_D01__GPMI_D1 0x0010 15 #define MX28_PAD_GPMI_D02__GPMI_D2 0x0020 16 #define MX28_PAD_GPMI_D03__GPMI_D3 0x0030 17 #define MX28_PAD_GPMI_D04__GPMI_D4 0x0040 18 #define MX28_PAD_GPMI_D05__GPMI_D5 0x0050 19 #define MX28_PAD_GPMI_D06__GPMI_D6 0x0060 20 #define MX28_PAD_GPMI_D07__GPMI_D7 0x0070 21 #define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100 22 #define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110 [all …]
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/linux/drivers/net/ethernet/renesas/ |
H A D | rswitch.h | 17 for (i = 0; i < RSWITCH_NUM_PORTS; i++) \ 23 for (; i-- > 0; ) \ 44 #define RSWITCH_TOP_OFFSET 0x00008000 45 #define RSWITCH_COMA_OFFSET 0x00009000 46 #define RSWITCH_ETHA_OFFSET 0x0000a000 /* with RMAC */ 47 #define RSWITCH_ETHA_SIZE 0x00002000 /* with RMAC */ 48 #define RSWITCH_GWCA0_OFFSET 0x00010000 49 #define RSWITCH_GWCA1_OFFSET 0x00012000 55 #define GWCA_INDEX 0 57 #define GWCA_IPV_NUM 0 [all …]
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/linux/drivers/clk/imx/ |
H A D | clk-imx8mn.c | 334 hws[IMX8MN_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mn_clocks_probe() 343 base = devm_of_iomap(dev, np, 0, NULL); in imx8mn_clocks_probe() 350 …hws[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_se… in imx8mn_clocks_probe() 351 …hws[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_s… in imx8mn_clocks_probe() 352 …hws[IMX8MN_VIDEO_PLL_REF_SEL] = imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2, pll_ref_sel… in imx8mn_clocks_probe() 353 …hws[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels,… in imx8mn_clocks_probe() 354 …hws[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, A… in imx8mn_clocks_probe() 355 …hws[IMX8MN_M7_ALT_PLL_REF_SEL] = imx_clk_hw_mux("m7_alt_pll_ref_sel", base + 0x74, 0, 2, pll_ref_s… in imx8mn_clocks_probe() 356 …hws[IMX8MN_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, A… in imx8mn_clocks_probe() 357 …hws[IMX8MN_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels… in imx8mn_clocks_probe() [all …]
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H A D | clk-imx8mm.c | 314 hws[IMX8MM_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mm_clocks_probe() 323 base = of_iomap(np, 0); in imx8mm_clocks_probe() 328 …hws[IMX8MM_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_se… in imx8mm_clocks_probe() 329 …hws[IMX8MM_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_s… in imx8mm_clocks_probe() 330 …hws[IMX8MM_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_s… in imx8mm_clocks_probe() 331 …hws[IMX8MM_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels,… in imx8mm_clocks_probe() 332 …hws[IMX8MM_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe() 333 …hws[IMX8MM_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe() 334 …hws[IMX8MM_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe() 335 …hws[IMX8MM_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels… in imx8mm_clocks_probe() [all …]
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H A D | clk-imx8mp.c | 416 anatop_base = devm_of_iomap(dev, np, 0, NULL); in imx8mp_clocks_probe() 422 ccm_base = devm_platform_ioremap_resource(pdev, 0); in imx8mp_clocks_probe() 433 hws[IMX8MP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mp_clocks_probe() 441 …hws[IMX8MP_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", anatop_base + 0x0, 0, 2, pll… in imx8mp_clocks_probe() 442 …hws[IMX8MP_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", anatop_base + 0x14, 0, 2, pl… in imx8mp_clocks_probe() 443 …hws[IMX8MP_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", anatop_base + 0x28, 0, 2, pl… in imx8mp_clocks_probe() 444 …hws[IMX8MP_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", anatop_base + 0x50, 0, 2, pll_re… in imx8mp_clocks_probe() 445 …hws[IMX8MP_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", anatop_base + 0x64, 0, 2, pll_ref_… in imx8mp_clocks_probe() 446 …hws[IMX8MP_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", anatop_base + 0x74, 0, 2, pll_ref_… in imx8mp_clocks_probe() 447 …hws[IMX8MP_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", anatop_base + 0x84, 0, 2, pll_ref_… in imx8mp_clocks_probe() [all …]
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H A D | clk-imx8mq.c | 298 hws[IMX8MQ_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mq_clocks_probe() 308 base = devm_of_iomap(dev, np, 0, NULL); in imx8mq_clocks_probe() 315 …hws[IMX8MQ_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x28, 16, 2, pll_ref_sels, … in imx8mq_clocks_probe() 316 …hws[IMX8MQ_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x18, 16, 2, pll_ref_sels, … in imx8mq_clocks_probe() 317 …hws[IMX8MQ_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x20, 16, 2, pll_ref_sels, … in imx8mq_clocks_probe() 318 …hws[IMX8MQ_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 16, 2, pll_ref_s… in imx8mq_clocks_probe() 319 …hws[IMX8MQ_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x8, 16, 2, pll_ref_s… in imx8mq_clocks_probe() 320 …hws[IMX8MQ_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x10, 16, 2, pll_ref_… in imx8mq_clocks_probe() 321 …hws[IMX8MQ_SYS3_PLL1_REF_SEL] = imx_clk_hw_mux("sys3_pll1_ref_sel", base + 0x48, 0, 2, pll_ref_sel… in imx8mq_clocks_probe() 322 …hws[IMX8MQ_DRAM_PLL1_REF_SEL] = imx_clk_hw_mux("dram_pll1_ref_sel", base + 0x60, 0, 2, pll_ref_sel… in imx8mq_clocks_probe() [all …]
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/linux/drivers/net/ethernet/marvell/octeontx2/af/ |
H A D | rvu_reg.h | 12 #define RVU_AF_MSIXTR_BASE (0x10) 13 #define RVU_AF_ECO (0x20) 14 #define RVU_AF_BLK_RST (0x30) 15 #define RVU_AF_PF_BAR4_ADDR (0x40) 16 #define RVU_AF_RAS (0x100) 17 #define RVU_AF_RAS_W1S (0x108) 18 #define RVU_AF_RAS_ENA_W1S (0x110) 19 #define RVU_AF_RAS_ENA_W1C (0x118) 20 #define RVU_AF_GEN_INT (0x120) 21 #define RVU_AF_GEN_INT_W1S (0x128) [all …]
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/linux/drivers/scsi/qla2xxx/ |
H A D | qla_dbg.c | 13 * | Module Init and Probe | 0x0199 | | 14 * | Mailbox commands | 0x1206 | 0x11a5-0x11ff | 15 * | Device Discovery | 0x2134 | 0x2112-0x2115 | 16 * | | | 0x2127-0x2128 | 17 * | Queue Command and IO tracing | 0x3074 | 0x300b | 18 * | | | 0x3027-0x3028 | 19 * | | | 0x303d-0x3041 | 20 * | | | 0x302e,0x3033 | 21 * | | | 0x3036,0x3038 | 22 * | | | 0x303a | [all …]
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/linux/arch/arm64/boot/dts/ti/ |
H A D | k3-am65-main.dtsi | 12 reg = <0x0 0x70000000 0x0 0x200000>; 15 ranges = <0x0 0x0 0x70000000 0x200000>; 17 atf-sram@0 { 18 reg = <0x0 0x20000>; 22 reg = <0xf0000 0x10000>; 26 reg = <0x100000 0x100000>; 37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 38 <0x00 0x01880000 0x00 0x90000>, /* GICR */ 39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ [all …]
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/linux/sound/soc/mediatek/mt8195/ |
H A D | mt8195-reg.h | 13 #define AFE_SRAM_BASE (0x10880000) 14 #define AFE_SRAM_SIZE (0x10000) 16 #define AUDIO_TOP_CON0 (0x0000) 17 #define AUDIO_TOP_CON1 (0x0004) 18 #define AUDIO_TOP_CON2 (0x0008) 19 #define AUDIO_TOP_CON3 (0x000c) 20 #define AUDIO_TOP_CON4 (0x0010) 21 #define AUDIO_TOP_CON5 (0x0014) 22 #define AUDIO_TOP_CON6 (0x0018) 23 #define AFE_MAS_HADDR_MSB (0x0020) [all …]
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/linux/sound/soc/mediatek/mt8188/ |
H A D | mt8188-reg.h | 14 #define AUDIO_TOP_CON0 (0x0000) 15 #define AUDIO_TOP_CON1 (0x0004) 16 #define AUDIO_TOP_CON2 (0x0008) 17 #define AUDIO_TOP_CON3 (0x000c) 18 #define AUDIO_TOP_CON4 (0x0010) 19 #define AUDIO_TOP_CON5 (0x0014) 20 #define AUDIO_TOP_CON6 (0x0018) 21 #define AFE_MAS_HADDR_MSB (0x0020) 22 #define AFE_MEMIF_ONE_HEART (0x0024) 23 #define AFE_MUX_SEL_CFG (0x0044) [all …]
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/linux/drivers/gpu/drm/amd/include/asic_reg/dce/ |
H A D | dce_6_0_d.h | 26 #define ixATTR00 0x0000 27 #define ixATTR01 0x0001 28 #define ixATTR02 0x0002 29 #define ixATTR03 0x0003 30 #define ixATTR04 0x0004 31 #define ixATTR05 0x0005 32 #define ixATTR06 0x0006 33 #define ixATTR07 0x0007 34 #define ixATTR08 0x0008 35 #define ixATTR09 0x0009 [all …]
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H A D | dce_8_0_d.h | 27 #define mmPIPE0_PG_CONFIG 0x1760 28 #define mmPIPE0_PG_ENABLE 0x1761 29 #define mmPIPE0_PG_STATUS 0x1762 30 #define mmPIPE1_PG_CONFIG 0x1764 31 #define mmPIPE1_PG_ENABLE 0x1765 32 #define mmPIPE1_PG_STATUS 0x1766 33 #define mmPIPE2_PG_CONFIG 0x1768 34 #define mmPIPE2_PG_ENABLE 0x1769 35 #define mmPIPE2_PG_STATUS 0x176a 36 #define mmPIPE3_PG_CONFIG 0x176c [all …]
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H A D | dce_11_0_d.h | 27 #define mmPIPE0_PG_CONFIG 0x2c0 28 #define mmPIPE0_PG_ENABLE 0x2c1 29 #define mmPIPE0_PG_STATUS 0x2c2 30 #define mmPIPE1_PG_CONFIG 0x2c3 31 #define mmPIPE1_PG_ENABLE 0x2c4 32 #define mmPIPE1_PG_STATUS 0x2c5 33 #define mmPIPE2_PG_CONFIG 0x2c6 34 #define mmPIPE2_PG_ENABLE 0x2c7 35 #define mmPIPE2_PG_STATUS 0x2c8 36 #define mmDCFEV0_PG_CONFIG 0x2db [all …]
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H A D | dce_10_0_d.h | 27 #define mmPIPE0_PG_CONFIG 0x2c0 28 #define mmPIPE0_PG_ENABLE 0x2c1 29 #define mmPIPE0_PG_STATUS 0x2c2 30 #define mmPIPE1_PG_CONFIG 0x2c3 31 #define mmPIPE1_PG_ENABLE 0x2c4 32 #define mmPIPE1_PG_STATUS 0x2c5 33 #define mmPIPE2_PG_CONFIG 0x2c6 34 #define mmPIPE2_PG_ENABLE 0x2c7 35 #define mmPIPE2_PG_STATUS 0x2c8 36 #define mmPIPE3_PG_CONFIG 0x2c9 [all …]
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H A D | dce_11_2_d.h | 27 #define mmPIPE0_PG_CONFIG 0x2c0 28 #define mmPIPE0_PG_ENABLE 0x2c1 29 #define mmPIPE0_PG_STATUS 0x2c2 30 #define mmPIPE1_PG_CONFIG 0x2c3 31 #define mmPIPE1_PG_ENABLE 0x2c4 32 #define mmPIPE1_PG_STATUS 0x2c5 33 #define mmPIPE2_PG_CONFIG 0x2c6 34 #define mmPIPE2_PG_ENABLE 0x2c7 35 #define mmPIPE2_PG_STATUS 0x2c8 36 #define mmPIPE3_PG_CONFIG 0x2c9 [all …]
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/linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
H A D | gc_11_0_0_offset.h | 29 // base address: 0x4980 30 …SDMA0_DEC_START 0x0000 31 …e regSDMA0_DEC_START_BASE_IDX 0 32 …SDMA0_F32_MISC_CNTL 0x000b 33 …e regSDMA0_F32_MISC_CNTL_BASE_IDX 0 34 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f 35 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0 36 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0010 37 …e regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX 0 38 …SDMA0_POWER_CNTL 0x001a [all …]
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H A D | gc_11_0_3_offset.h | 29 // base address: 0x4980 30 …SDMA0_DEC_START 0x0000 31 …e regSDMA0_DEC_START_BASE_IDX 0 32 …SDMA0_F32_MISC_CNTL 0x000b 33 …e regSDMA0_F32_MISC_CNTL_BASE_IDX 0 34 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f 35 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0 36 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0010 37 …e regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX 0 38 …SDMA0_POWER_CNTL 0x001a [all …]
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/linux/drivers/net/wireless/realtek/rtw89/ |
H A D | rtw8851b_table.c | 10 {0x704, 0x601E0500}, 11 {0x4000, 0x00000000}, 12 {0x4004, 0xCA014000}, 13 {0x4008, 0xC751D4F0}, 14 {0x400C, 0x44511475}, 15 {0x4010, 0x00000000}, 16 {0x4014, 0x00000000}, 17 {0x47BC, 0x00000380}, 18 {0x4018, 0x4F4C084B}, 19 {0x401C, 0x084A4E52}, [all …]
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H A D | rtw8852b_table.c | 10 {0x704, 0x601E0100}, 11 {0x4000, 0x00000000}, 12 {0x4004, 0xCA014000}, 13 {0x4008, 0xC751D4F0}, 14 {0x400C, 0x44511475}, 15 {0x4010, 0x00000000}, 16 {0x4014, 0x00000000}, 17 {0x4018, 0x4F4C084B}, 18 {0x401C, 0x084A4E52}, 19 {0x4020, 0x4D504E4B}, [all …]
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