Lines Matching +full:0 +full:x40c0

49   "^mux-controller@[0-9a-f]+$":
54   "^clock-controller@[0-9a-f]+$":
60   "phy@[0-9a-f]+$":
66   "^chipid@[0-9a-f]+$":
72   "^pcie-ctrl@[0-9a-f]+$":
77   "^clock@[0-9a-f]+$":
83   "^dss-oldi-io-ctrl@[0-9a-f]+$":
102         reg = <0x00100000 0x1c000>;
109             reg = <0x00004080 0x50>;
113                 <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
114                 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
115                 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
116                 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
117                 <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
123             reg = <0x4140 0x18>;
129             reg = <0x14 0x4>;
134             reg = <0x4070 0x4>;