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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dnxp,lpc1850-dwmac.txt13 reg = <0x40010000 0x2000>;
H A Dnxp,lpc1850-dwmac.yaml73 reg = <0x40010000 0x2000>;
H A Dsnps,dwc-qos-ethernet.txt125 - #size-cells: Must be <0>.
143 interrupts = <0x0 0x1e 0x4>;
144 reg = <0x40010000 0x4000>;
153 snps,burst-map = <0x7>;
160 #address-cells = <0x1>;
161 #size-cells = <0x
[all...]
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dnxp,lpc3220-mic.txt25 reg = <0x40008000 0x4000>;
32 reg = <0x4000c000 0x4000>;
37 interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
43 reg = <0x40010000 0x4000>;
55 reg = <0x40048000 0x1000>;
/freebsd/sys/contrib/device-tree/Bindings/reset/
H A Dnxp,lpc1850-rgu.txt67 reg = <0x40053000 0x1000>;
76 reg = <0x40010000 0x2000>;
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dspear310.dtsi15 ranges = <0x40000000 0x40000000 0x10000000
16 0xb0000000 0xb0000000 0x10000000
17 0xd0000000 0xd0000000 0x30000000>;
21 reg = <0xb4000000 0x1000>;
29 reg = <0x44000000 0x1000 /* FSMC Register */
30 0x40000000 0x0010 /* NAND Base DATA */
31 0x40020000 0x0010 /* NAND Base ADDR */
32 0x40010000 0x0010>; /* NAND Base CMD */
39 reg = <0xb4000000 0x1000>;
49 ranges = <0xb0000000 0xb0000000 0x10000000
[all …]
H A Dstm32f746.dtsi54 #clock-cells = <0>;
56 clock-frequency = <0>;
60 #clock-cells = <0>;
66 #clock-cells = <0>;
72 #clock-cells = <0>;
81 #size-cells = <0>;
83 reg = <0x40000000 0x400>;
84 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
103 #size-cells = <0>;
105 reg = <0x40000400 0x400>;
[all …]
H A Dstm32f429.dtsi58 #clock-cells = <0>;
60 clock-frequency = <0>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
76 #clock-cells = <0>;
78 clock-frequency = <0>;
85 reg = <0x1fff7800 0x400>;
89 reg = <0x22c 0x2>;
92 reg = <0x22e 0x2>;
98 #size-cells = <0>;
[all …]
H A Dstm32mp131.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
21 reg = <0>;
43 #size-cells = <0>;
44 linaro,optee-channel-id = <0>;
47 reg = <0x14>;
52 reg = <0x16>;
57 reg = <0x17>;
61 #size-cells = <0>;
63 scmi_reg11: regulator@0 {
[all …]
H A Dstm32mp151.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
22 reg = <0>;
42 reg = <0xa0021000 0x1000>,
43 <0xa0022000 0x2000>;
58 #clock-cells = <0>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
76 #clock-cells = <0>;
82 #clock-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dste-dma40.txt20 reg = <0x801C0000 0x1000 0x40010000 0x800>;
23 interrupts = <0 25 0x4>;
43 0x00000001: Mode:
46 0x00000002: Direction:
49 0x00000004: Endianness:
52 0x00000008: Use fixed channel:
55 0x00000010: Set channel as high priority:
62 0: SPI controller 0
63 1: SD/MMC controller 0 (unused)
75 13: UART port 0
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6qdl-zii-rdu2.dtsi22 #size-cells = <0>;
24 pinctrl-0 = <&pinctrl_mdio1>;
28 phy: ethernet-phy@0 {
29 pinctrl-0 = <&pinctrl_rmii_phy_irq>;
31 reg = <0>;
84 pinctrl-0 = <&pinctrl_reg_3p3v_sd>;
177 #size-cells = <0>;
180 pinctrl-0 = <&pinctrl_disp0>;
183 port@0 {
184 reg = <0>;
[all …]
H A Dimx6qp-prtwd3.dts21 reg = <0x10000000 0x20000000>;
26 reg = <0x80000000 0x20000000>;
31 #clock-cells = <0>;
37 #clock-cells = <0>;
43 #clock-cells = <0>;
49 #clock-cells = <0>;
56 pinctrl-0 = <&pinctrl_mdio>;
59 #size-cells = <0>;
65 reg = <0x3>;
73 micrel,led-mode = <0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/lpc/
H A Dlpc32xx.dtsi20 #size-cells = <0>;
22 cpu@0 {
25 reg = <0x0>;
32 #clock-cells = <0>;
39 #clock-cells = <0>;
49 ranges = <0x00000000 0x00000000 0x10000000>,
50 <0x20000000 0x20000000 0x30000000>,
51 <0xe0000000 0xe0000000 0x04000000>;
55 reg = <0x08000000 0x20000>;
59 ranges = <0x00000000 0x08000000 0x20000>;
[all …]
H A Dlpc18xx.dtsi19 #define LPC_PIN(port, pin) (0x##port * 32 + pin)
28 #size-cells = <0>;
30 cpu@0 {
33 reg = <0x0>;
41 #clock-cells = <0>;
47 #clock-cells = <0>;
53 #clock-cells = <0>;
54 clock-frequency = <0>;
60 #clock-cells = <0>;
61 clock-frequency = <0>;
[all...]
/freebsd/sys/x86/xen/
H A Dpv.c137 xen = 0; in isxen()
138 for (base = 0x40000000; base < 0x40010000; base += 0x100) { in isxen()
154 } while (0)
179 if (start_info->memmap_paddr != 0) in hammer_time_xen()
185 if (start_info->modlist_paddr != 0) { in hammer_time_xen()
188 if (start_info->nr_modules == 0) { in hammer_time_xen()
190 "ERROR: modlist_paddr != 0 but nr_modules == 0\n"); in hammer_time_xen()
194 for (i = 0; i < start_info->nr_modules; i++) in hammer_time_xen()
204 return (hammer_time(0, physfree)); in hammer_time_xen()
237 if (shdr[i].sh_offset == 0) in xen_pvh_parse_symtab()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/st/
H A Dstm32mp251.dtsi18 #size-cells = <0>;
20 cpu0: cpu@0 {
23 reg = <0>;
39 arm,smc-id = <0xb200005a>;
45 #clock-cells = <0>;
47 clock-frequency = <0>;
51 #clock-cells = <0>;
68 #size-cells = <0>;
69 linaro,optee-channel-id = <0>;
72 reg = <0x14>;
[all …]
/freebsd/sys/x86/x86/
H A Didentcpu.c75 #define IDENTBLUE_CYRIX486 0
114 /* leaf 7 %ecx = 0 */
134 &via_feature_rng, 0,
137 &via_feature_xcrypt, 0,
154 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch) in sysctl_hw_machine()
163 CTLFLAG_CAPRD | CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class");
171 cpu_model, 0, "Machine model");
175 &hw_clockrate, 0, "CPU instruction clock rate");
181 0, "Hypervisor vendor");
242 #if 0
[all …]
/freebsd/tools/test/iconv/ref/
H A DUTF-32BE-rev1 0x00 = 0x00000000
2 0x01 = 0x01000000
3 0x02 = 0x02000000
4 0x03 = 0x03000000
5 0x04 = 0x04000000
6 0x05 = 0x05000000
7 0x06 = 0x06000000
8 0x07 = 0x07000000
9 0x08 = 0x08000000
10 0x09 = 0x09000000
[all …]
/freebsd/sys/contrib/dev/rtw88/
H A Drtw8822c_table.c16 0x83000000, 0x00000000, 0x40000000, 0x00000000,
17 0x1D90, 0x300001FF,
18 0x1D90, 0x300101FE,
19 0x1D90, 0x300201F
[all...]