Lines Matching +full:0 +full:x40010000
22 #size-cells = <0>;
24 pinctrl-0 = <&pinctrl_mdio1>;
28 phy: ethernet-phy@0 {
29 pinctrl-0 = <&pinctrl_rmii_phy_irq>;
31 reg = <0>;
84 pinctrl-0 = <&pinctrl_reg_3p3v_sd>;
177 #size-cells = <0>;
180 pinctrl-0 = <&pinctrl_disp0>;
183 port@0 {
184 reg = <0>;
202 #clock-cells = <0>;
208 #clock-cells = <0>;
209 clock-frequency = <0>;
214 #clock-cells = <0>;
250 lvds-channel@0 {
263 pinctrl-0 = <&pinctrl_uart1>;
269 pinctrl-0 = <&pinctrl_uart3>;
277 pinctrl-0 = <&pinctrl_uart4>;
300 reg = <0xa3 0x4000>;
308 reg = <0xa4 0x4000>;
318 pinctrl-0 = <&pinctrl_ecspi1>;
322 flash@0 {
325 reg = <0>;
331 pinctrl-0 = <&pinctrl_gpio3_hog>;
364 pinctrl-0 = <&pinctrl_i2c1>;
371 pinctrl-0 = <&pinctrl_codec2>;
372 reg = <0x18>;
373 #sound-dai-cells = <0>;
385 pinctrl-0 = <&pinctrl_accel>;
387 reg = <0x1c>;
398 pinctrl-0 = <&pinctrl_tpa2>;
399 reg = <0x60>;
408 pinctrl-0 = <&pinctrl_tc358767>;
409 reg = <0x68>;
417 #size-cells = <0>;
432 pinctrl-0 = <&pinctrl_i2c2>;
439 pinctrl-0 = <&pinctrl_pfuze100_irq>;
440 reg = <0x08>;
529 reg = <0x38>;
534 reg = <0x48>;
539 reg = <0x4e>;
540 #clock-cells = <0>;
549 reg = <0x54>;
554 reg = <0x68>;
560 pinctrl-0 = <&pinctrl_i2c3>;
567 pinctrl-0 = <&pinctrl_codec1>;
568 reg = <0x18>;
569 #sound-dai-cells = <0>;
576 reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
582 pinctrl-0 = <&pinctrl_ts>;
583 reg = <0x20>;
590 #size-cells = <0>;
593 reg = <0x1>;
598 reg = <0x11>;
607 reg = <0x12>;
617 pinctrl-0 = <&pinctrl_ts>;
618 reg = <0x2a>;
629 pinctrl-0 = <&pinctrl_ucs1002_pins>;
630 reg = <0x32>;
639 pinctrl-0 = <&pinctrl_tpa1>;
640 reg = <0x60>;
653 pinctrl-0 = <&pinctrl_pcie>;
657 host@0 {
658 reg = <0 0 0 0 0>;
663 i210: i210@0 {
664 reg = <0 0 0 0 0>;
671 pinctrl-0 = <&pinctrl_usdhc2>;
684 pinctrl-0 = <&pinctrl_usdhc3>;
686 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
697 pinctrl-0 = <&pinctrl_usdhc4>;
715 pinctrl-0 = <&pinctrl_enet>;
725 #size-cells = <0>;
730 switch: switch@0 {
732 pinctrl-0 = <&pinctrl_switch_irq>;
734 reg = <0>;
735 dsa,member = <0 0>;
744 #size-cells = <0>;
746 port@0 {
747 reg = <0>;
784 #size-cells = <0>;
786 switchphy0: switchphy@0 {
787 reg = <0>;
789 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
848 pinctrl-0 = <&pinctrl_audmux>;
852 fsl,audmux-port = <0>;
867 IMX_AUDMUX_V2_PDCR_RXDSEL(0)
895 MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x4001b000
901 MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
902 MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0
903 MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
904 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
905 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130b0
906 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
912 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x40000038
918 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x40000038
924 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100f9
925 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100f9
926 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100f9
927 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100f9
928 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100f9
929 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100f9
930 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100f9
931 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100f9
932 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100f9
933 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100f9
934 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100f9
935 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100f9
936 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100f9
937 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100f9
938 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100f9
939 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100f9
940 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100f9
941 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100f9
942 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100f9
943 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100f9
944 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100f9
945 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100f9
946 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x100f9
947 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x100f9
948 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x100f9
949 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x100f9
950 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x100f9
951 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x100f9
957 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
958 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
959 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
960 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b1
966 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x000b1
967 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b1
968 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x100f5
969 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x100f5
970 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x100c0
971 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x100c0
972 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x100f5
973 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x100f5
974 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x40010040
975 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x100b0
976 MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0
982 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
983 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0
984 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
985 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0
991 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b811
992 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b811
998 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b811
999 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b811
1005 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b811
1006 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b811
1013 MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x4001b030
1014 MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x40018830
1020 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x10038
1026 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x40010000
1032 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x858
1038 MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x40010000
1044 MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x4001b000
1050 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x10
1056 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x40000038
1062 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x40000038
1068 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
1069 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0
1075 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
1076 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
1082 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
1083 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
1084 MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
1090 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
1091 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
1097 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0
1098 MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x1b0b0
1104 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x10059
1105 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10069
1106 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
1107 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
1108 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
1109 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
1110 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x40010040
1116 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x10059
1117 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10069
1118 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1119 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1120 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1121 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1122 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x40010040
1129 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
1130 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
1131 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
1132 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
1133 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
1134 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
1135 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
1136 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
1137 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
1138 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
1139 MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x1b0b1