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Searched +full:0 +full:x4000c000 (Results 1 – 5 of 5) sorted by relevance

/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dnxp,lpc3220-mic.txt25 reg = <0x40008000 0x4000>;
32 reg = <0x4000c000 0x4000>;
37 interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
43 reg = <0x40010000 0x4000>;
55 reg = <0x40048000 0x1000>;
/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,r9a06g032-sysctrl.yaml40 const: 0
67 reg = <0x4000c000 0x1000>;
72 #power-domain-cells = <0>;
/linux/arch/arm/boot/dts/nxp/lpc/
H A Dlpc32xx.dtsi20 #size-cells = <0>;
22 cpu@0 {
25 reg = <0x0>;
32 #clock-cells = <0>;
39 #clock-cells = <0>;
49 ranges = <0x00000000 0x00000000 0x10000000>,
50 <0x20000000 0x20000000 0x30000000>,
51 <0xe0000000 0xe0000000 0x04000000>;
55 reg = <0x08000000 0x20000>;
59 ranges = <0x00000000 0x08000000 0x20000>;
[all …]
/linux/arch/arm/boot/dts/renesas/
H A Dr9a06g032.dtsi19 #size-cells = <0>;
21 cpu@0 {
24 reg = <0>;
34 cpu-release-addr = <0 0x4000c204>;
39 #clock-cells = <0>;
41 clock-frequency = <0>;
45 #clock-cells = <0>;
51 #clock-cells = <0>;
53 clock-frequency = <0>;
57 #clock-cells = <0>;
[all …]
/linux/arch/arm/mach-lpc32xx/
H A Dlpc32xx.h17 * AHB 0 physical base addresses
19 #define LPC32XX_SLC_BASE 0x20020000
20 #define LPC32XX_SSP0_BASE 0x20084000
21 #define LPC32XX_SPI1_BASE 0x20088000
22 #define LPC32XX_SSP1_BASE 0x2008C000
23 #define LPC32XX_SPI2_BASE 0x20090000
24 #define LPC32XX_I2S0_BASE 0x20094000
25 #define LPC32XX_SD_BASE 0x20098000
26 #define LPC32XX_I2S1_BASE 0x2009C000
27 #define LPC32XX_MLC_BASE 0x200A8000
[all …]