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/linux/Documentation/devicetree/bindings/memory-controllers/
H A Darm,pl172.yaml58 "^cs[0-9]$":
62 "^flash@[0-9],[0-9a-f]+$":
67 "^(gpio|sram)@[0-9],[0-9a-f]+$":
187 reg = <0x40005000 0x1000>;
192 ranges = <0 0 0x1c000000 0x1000000
193 1 0 0x1d000000 0x1000000
194 2 0 0x1e000000 0x1000000
195 3 0 0x1f000000 0x1000000>;
202 mpmc,cs = <0>;
205 mpmc,write-enable-delay = <0>;
[all …]
/linux/arch/riscv/boot/dts/sophgo/
H A Dsg2044.dtsi20 reg = <0x00000000 0x80000000 0x00000010 0x00000000>;
26 #clock-cells = <0>;
37 reg = <0x6c 0x00000000 0x0 0x00001000>,
38 <0x6c 0x00300000 0x0 0x00004000>,
39 <0x48 0x00000000 0x0 0x00001000>,
40 <0x6c 0x000c0000 0x0 0x00001000>;
48 interrupt-map-mask = <0 0 0 7>;
49 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
50 <0 0 0 2 &pcie_intc0 1>,
51 <0 0 0 3 &pcie_intc0 2>,
[all …]
/linux/arch/arm/boot/dts/st/
H A Dstm32f746.dtsi54 #clock-cells = <0>;
56 clock-frequency = <0>;
60 #clock-cells = <0>;
66 #clock-cells = <0>;
72 #clock-cells = <0>;
81 #size-cells = <0>;
83 reg = <0x40000000 0x400>;
84 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
103 #size-cells = <0>;
105 reg = <0x40000400 0x400>;
[all …]
H A Dstm32f429.dtsi58 #clock-cells = <0>;
60 clock-frequency = <0>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
76 #clock-cells = <0>;
78 clock-frequency = <0>;
85 reg = <0x1fff7800 0x400>;
89 reg = <0x22c 0x2>;
92 reg = <0x22e 0x2>;
98 #size-cells = <0>;
[all …]