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/linux/Documentation/sound/cards/
H A Dserial-u16550.rst7 * 0 - Roland Soundcanvas support (default)
28 /sbin/modprobe snd-serial-u16550 port=0x3f8 irq=4 speed=115200
34 /sbin/modprobe snd-serial-u16550 port=0x3f8 irq=4 outs=4
45 /sbin/modprobe snd-serial-u16550 port=0x3f8 irq=4 adaptor=1 \
56 /sbin/modprobe snd-serial-u16550 port=0x3f8 irq=4 adaptor=2
73 /sbin/modprobe snd-serial-u16550 port=0x3f8 irq=4 adaptor=3
/linux/arch/x86/boot/
H A Dearly_serial_console.c8 #define DEFAULT_SERIAL_PORT 0x3f8 /* ttyS0 */
10 #define DLAB 0x80
12 #define TXR 0 /* Transmit register (WRITE) */
13 #define RXR 0 /* Receive register (READ) */
21 #define DLL 0 /* Divisor Latch Low */
31 outb(0x3, port + LCR); /* 8n1 */ in early_serial_init()
32 outb(0, port + IER); /* no interrupt */ in early_serial_init()
33 outb(0, port + FCR); /* no fifo */ in early_serial_init()
34 outb(0x3, port + MCR); /* DTR + RTS */ in early_serial_init()
39 outb(divisor & 0xff, port + DLL); in early_serial_init()
[all …]
/linux/arch/mips/loongson2ef/common/
H A Duart_base.c25 loongson_uart_base = LOONGSON_PCIIO_BASE + 0x3f8; in prom_init_loongson_uart_base()
29 loongson_uart_base = LOONGSON_PCIIO_BASE + 0x2f8; in prom_init_loongson_uart_base()
37 loongson_uart_base = LOONGSON_LIO1_BASE + 0x3f8; in prom_init_loongson_uart_base()
42 setup_8250_early_printk_port(_loongson_uart_base, 0, 1024); in prom_init_loongson_uart_base()
/linux/arch/arm/mach-mediatek/
H A Dplatsmp.c17 #define MTK_SMP_REG_SIZE 0x1000
27 0x80002000, 0x3fc,
28 { 0x534c4131, 0x4c415332, 0x41534c33 },
29 { 0x3f8, 0x3f8, 0x3f8 },
33 0x10002000, 0x34,
34 { 0x534c4131, 0x4c415332, 0x41534c33 },
35 { 0x38, 0x3c, 0x40 },
39 0x10202000, 0x34,
40 { 0x534c4131, 0x4c415332, 0x41534c33 },
41 { 0x38, 0x3c, 0x40 },
[all …]
/linux/arch/arm/mach-footbridge/
H A Disa.c16 [0] = {
17 .start = 0x70,
18 .end = 0x73,
36 [0] = {
37 .start = 0x3f8,
38 .end = 0x3ff,
42 .start = 0x2f8,
43 .end = 0x2ff,
50 .iobase = 0x3f8,
53 .regshift = 0,
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
H A Dimx51-pinfunc.h13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
[all …]
/linux/drivers/media/common/b2c2/
H A Dflexcop-eeprom.c9 #if 0
13 return flex_i2c_write(adapter, 0x20000000, 0x50, addr, buf, len);
21 for (i = 0; i < retries; i++) {
27 return 0;
38 return 0;
41 wbuf[16] = 0;
42 wbuf[17] = 0;
43 wbuf[18] = 0;
45 return eeprom_lrc_write(adapter, 0x3e4, 20, wbuf, rbuf, 4);
53 return 0;
[all …]
/linux/drivers/media/platform/ti/davinci/
H A Dvpif.c3 * VPIF is a receiver and transmitter for video data. It has two channels(0, 1)
69 .ycmux_mode = 0,
76 .capture_format = 0,
77 .vbi_supported = 0,
86 .ycmux_mode = 0,
93 .capture_format = 0,
94 .vbi_supported = 0,
103 .ycmux_mode = 0,
110 .capture_format = 0,
111 .vbi_supported = 0,
[all …]
/linux/arch/sparc/include/asm/
H A Dintr_queue.h7 #define INTRQ_CPU_MONDO_HEAD 0x3c0 /* CPU mondo head */
8 #define INTRQ_CPU_MONDO_TAIL 0x3c8 /* CPU mondo tail */
9 #define INTRQ_DEVICE_MONDO_HEAD 0x3d0 /* Device mondo head */
10 #define INTRQ_DEVICE_MONDO_TAIL 0x3d8 /* Device mondo tail */
11 #define INTRQ_RESUM_MONDO_HEAD 0x3e0 /* Resumable error mondo head */
12 #define INTRQ_RESUM_MONDO_TAIL 0x3e8 /* Resumable error mondo tail */
13 #define INTRQ_NONRESUM_MONDO_HEAD 0x3f0 /* Non-resumable error mondo head */
14 #define INTRQ_NONRESUM_MONDO_TAIL 0x3f8 /* Non-resumable error mondo head */
/linux/arch/mips/sni/
H A Dpcit.c32 PORT(0x3f8, 0),
33 PORT(0x2f8, 3),
46 PORT(0x3f8, 0),
47 PORT(0x2f8, 3),
48 PORT(0x3e8, 4),
49 PORT(0x2e8, 3),
63 .start = 0x70,
64 .end = 0x71,
86 .start = 0x00000000UL,
87 .end = 0x03bfffffUL,
[all …]
/linux/drivers/tty/serial/8250/
H A D8250_early.c17 * earlycon=uart8250,io,0x3f8,9600n8
18 * earlycon=uart8250,mmio,0xff5e0000,115200n8
19 * earlycon=uart8250,mmio32,0xff5e0000,115200n8
21 * console=uart8250,io,0x3f8,9600n8
22 * console=uart8250,mmio,0xff5e0000,115200n8
23 * console=uart8250,mmio32,0xff5e0000,115200n8
52 return 0; in serial8250_early_in()
109 int num_read = 0; in early_serial8250_read()
134 serial8250_early_out(port, UART_FCR, 0); /* no fifo */ in init_port()
141 serial8250_early_out(port, UART_DLL, divisor & 0xff); in init_port()
[all …]
/linux/arch/alpha/include/asm/
H A Dserial.h27 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \
28 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \
29 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \
30 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */
/linux/arch/x86/include/asm/
H A Dserial.h17 # define STD_COM4_FLAGS (UPF_BOOT_AUTOCONF | 0 | UPF_AUTO_IRQ)
19 # define STD_COMX_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 0 )
20 # define STD_COM4_FLAGS (UPF_BOOT_AUTOCONF | 0 | 0 )
25 { .uart = 0, BASE_BAUD, 0x3F8, 4, STD_COMX_FLAGS }, /* ttyS0 */ \
26 { .uart = 0, BASE_BAUD, 0x2F8, 3, STD_COMX_FLAGS }, /* ttyS1 */ \
27 { .uart = 0, BASE_BAUD, 0x3E8, 4, STD_COMX_FLAGS }, /* ttyS2 */ \
28 { .uart = 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */
/linux/arch/m68k/include/asm/
H A Dserial.h32 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \
33 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \
34 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \
35 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */
H A Dapollohw.h52 #define IO_BASE 0x80000000
62 #define SAU7_SIO01_PHYSADDR 0x10400
63 #define SAU7_SIO23_PHYSADDR 0x10500
64 #define SAU7_RTC_PHYSADDR 0x10900
65 #define SAU7_PICA 0x11000
66 #define SAU7_PICB 0x11100
67 #define SAU7_CPUCTRL 0x10100
68 #define SAU7_TIMER 0x010800
70 #define SAU8_SIO01_PHYSADDR 0x8400
71 #define SAU8_RTC_PHYSADDR 0x8900
[all …]
/linux/drivers/char/mwave/
H A DREADME8 0x0001 mwavedd api tracing
9 0x0002 smapi api tracing
10 0x0004 3780i tracing
11 0x0008 tp3780i tracing
22 mwave_3780i_io=0x130/0x350/0x0070/0xDB0
32 mwave_uart_io=0x3f8/0x2f8/0x3E8/0x2E8
39 insmod mwave mwave_3780i_irq=10 mwave_3780i_io=0x0130 mwave_uart_irq=3 mwave_uart_io=0x2f8
/linux/arch/mips/mti-malta/
H A Dmalta-platform.c38 .regshift = 0, \
44 SMC_PORT(0x3F8, 4),
45 SMC_PORT(0x2F8, 3),
47 .mapbase = 0x1f000900, /* The CBUS UART */
/linux/Documentation/networking/device_drivers/hamradio/
H A Dbaycom.rst90 simple. Once installed, four interfaces named bc{sf,sh,p,e}[0-3] are available.
109 modprobe baycom_ser_fdx mode="ser12*" iobase=0x3f8 irq=4
110 sethdlc -i bcsf0 -p mode "ser12*" io 0x3f8 irq 4
116 insmod baycom_par mode="picpar" iobase=0x378
117 sethdlc -i bcp0 -p mode "picpar" io 0x378
133 the hardware (options=0).
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
H A Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
/linux/arch/powerpc/platforms/44x/
H A Dpci.h18 #define PCIX0_VENDID 0x000
19 #define PCIX0_DEVID 0x002
20 #define PCIX0_COMMAND 0x004
21 #define PCIX0_STATUS 0x006
22 #define PCIX0_REVID 0x008
23 #define PCIX0_CLS 0x009
24 #define PCIX0_CACHELS 0x00c
25 #define PCIX0_LATTIM 0x00d
26 #define PCIX0_HDTYPE 0x00e
27 #define PCIX0_BIST 0x00f
[all …]
/linux/arch/x86/kernel/
H A Dearly_printk.c24 #define VGABASE (__ISA_IO_base + 0xb8000)
34 while ((c = *str++) != '\0' && n-- > 0) { in early_vga_write()
37 for (k = 1, j = 0; k < max_ypos; k++, j++) { in early_vga_write()
38 for (i = 0; i < max_xpos; i++) { in early_vga_write()
43 for (i = 0; i < max_xpos; i++) in early_vga_write()
44 writew(0x720, VGABASE + 2*(max_xpos*j + i)); in early_vga_write()
49 if (current_xpos > 0) in early_vga_write()
52 current_xpos = 0; in early_vga_write()
56 current_xpos = 0; in early_vga_write()
59 writew(((0x7 << 8) | (unsigned short) c), in early_vga_write()
[all …]
/linux/include/linux/
H A Dtc.h29 #define TC_OLDCARD 0x3c0000
30 #define TC_NEWCARD 0x000000
32 #define TC_ROM_WIDTH 0x3e0
33 #define TC_ROM_STRIDE 0x3e4
34 #define TC_ROM_SIZE 0x3e8
35 #define TC_SLOT_SIZE 0x3ec
36 #define TC_PATTERN0 0x3f0
37 #define TC_PATTERN1 0x3f4
38 #define TC_PATTERN2 0x3f8
39 #define TC_PATTERN3 0x3fc
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Dam57xx-sbc-am57x.dts25 DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
26 DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
32 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
33 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
34 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
35 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
36 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
37 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
38 DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1_sdcd.gpio6_27 */
39 DRA7XX_CORE_IOPAD(0x377c, PIN_INPUT | MUX_MODE14) /* mmc1_sdwp.gpio6_28 */
[all …]

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