| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | idt,32434-pic.yaml | 43 reg = <0x3800c 0x0c>;
|
| /linux/drivers/crypto/intel/iaa/ |
| H A D | iaa_crypto_comp_fixed.c | 11 0x40030, 0x40031, 0x40032, 0x40033, 0x40034, 0x40035, 0x40036, 0x40037,
12 0x40038, 0x40039, 0x4003A, 0x4003B, 0x4003C, 0x4003D, 0x4003E, 0x4003F,
13 0x40040, 0x40041, 0x40042, 0x40043, 0x40044, 0x40045, 0x40046, 0x40047,
14 0x40048, 0x40049, 0x4004A, 0x4004B, 0x4004C, 0x4004D, 0x4004E, 0x4004F,
15 0x40050, 0x40051, 0x40052, 0x40053, 0x40054, 0x40055, 0x40056, 0x40057,
16 0x40058, 0x40059, 0x4005A, 0x4005B, 0x4005C, 0x4005D, 0x4005E, 0x4005F,
17 0x40060, 0x40061, 0x40062, 0x40063, 0x40064, 0x40065, 0x40066, 0x40067,
18 0x40068, 0x40069, 0x4006A, 0x4006B, 0x4006C, 0x4006D, 0x4006E, 0x4006F,
19 0x40070, 0x40071, 0x40072, 0x40073, 0x40074, 0x40075, 0x40076, 0x40077,
20 0x40078, 0x40079, 0x4007A, 0x4007B, 0x4007C, 0x4007D, 0x4007E, 0x4007F,
[all …]
|
| /linux/drivers/clk/qcom/ |
| H A D | gcc-qcm2290.c | 46 { 500000000, 1250000000, 0 },
58 .offset = 0x0,
61 .enable_reg = 0x79000,
62 .enable_mask = BIT(0),
75 { 0x1, 2 },
80 .offset = 0x0,
95 .offset = 0x1000,
98 .enable_reg = 0x79000,
113 .l = 0x3c,
114 .alpha = 0x0,
[all …]
|
| H A D | gcc-sm6115.c | 50 { 500000000, 1250000000, 0 },
58 .offset = 0x0,
63 .enable_reg = 0x79000,
64 .enable_mask = BIT(0),
77 { 0x1, 2 },
82 .offset = 0x0,
97 { 0x0, 1 },
102 .offset = 0x0,
118 .l = 0x3c,
119 .vco_val = 0x1 << 20,
[all …]
|
| H A D | gcc-sm6375.c | 54 { 249600000, 2000000000, 0 },
58 { 595200000, 3600000000UL, 0 },
62 .offset = 0x0,
65 .enable_reg = 0x79000,
66 .enable_mask = BIT(0),
79 { 0x1, 2 },
84 .offset = 0x0,
101 { 0x3, 3 },
106 .offset = 0x0,
123 .offset = 0x1000,
[all …]
|
| H A D | gcc-shikra.c | 67 { 500000000, 1250000000, 0 },
79 .offset = 0x0,
82 .enable_reg = 0x79000,
83 .enable_mask = BIT(0),
96 { 0x1, 2 },
101 .offset = 0x0,
119 .l = 0x3c,
120 .alpha = 0x0,
123 .main_output_mask = BIT(0),
124 .config_ctl_val = 0x4001055b,
[all …]
|
| H A D | negcc-nord.c | 46 .offset = 0x0,
49 .enable_reg = 0x0,
50 .enable_mask = BIT(0),
63 { 0x1, 2 },
68 .offset = 0x0,
85 .offset = 0x2000,
88 .enable_reg = 0x0,
102 { P_BI_TCXO, 0 },
112 { P_BI_TCXO, 0 },
124 { P_BI_TCXO, 0 },
[all …]
|
| H A D | gcc-sm6125.c | 42 .offset = 0x0,
45 .enable_reg = 0x79000,
46 .enable_mask = BIT(0),
85 .offset = 0x3000,
88 .enable_reg = 0x79000,
102 .offset = 0x4000,
105 .enable_reg = 0x79000,
119 .offset = 0x5000,
122 .enable_reg = 0x79000,
136 .offset = 0x6000,
[all …]
|
| H A D | gcc-ipq5332.c | 52 .offset = 0x20000,
55 .enable_reg = 0xb000,
56 .enable_mask = BIT(0),
79 .offset = 0x20000,
92 .offset = 0x21000,
95 .enable_reg = 0xb000,
107 .offset = 0x21000,
120 .offset = 0x22000,
123 .enable_reg = 0xb000,
135 .offset = 0x22000,
[all …]
|
| H A D | gcc-ipq9650.c | 51 .offset = 0x20000,
54 .enable_reg = 0xb000,
55 .enable_mask = BIT(0),
79 .offset = 0x20000,
92 .offset = 0x21000,
95 .enable_reg = 0xb000,
107 { 0x1, 2 },
112 .offset = 0x21000,
129 .offset = 0x22000,
132 .enable_reg = 0xb000,
[all …]
|
| /linux/drivers/gpu/drm/amd/include/asic_reg/nbif/ |
| H A D | nbif_6_1_offset.h | 26 // base address: 0x0
27 … 0x0000 // duplicate
28 … 0x0002 // duplicate
29 … 0x0004 // duplicate
30 … 0x0006 // duplicate
31 … 0x0008 // duplicate
32 … 0x0009 // duplicate
33 … 0x000a // duplicate
34 … 0x000b // duplicate
35 … 0x000c // duplicate
[all …]
|