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/linux/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A Dgaudi_blocks.h16 #define mmNIC0_PHY0_BASE 0x0ull
17 #define NIC0_PHY0_MAX_OFFSET 0x9F13
18 #define mmMME0_ACC_BASE 0x7FFC020000ull
19 #define MME0_ACC_MAX_OFFSET 0x5C00
20 #define MME0_ACC_SECTION 0x20000
21 #define mmMME0_SBAB_BASE 0x7FFC040000ull
22 #define MME0_SBAB_MAX_OFFSET 0x5800
23 #define MME0_SBAB_SECTION 0x1000
24 #define mmMME0_PRTN_BASE 0x7FFC041000ull
25 #define MME0_PRTN_MAX_OFFSET 0x5000
[all …]
/linux/drivers/s390/cio/
H A Ddevice_id.c31 * diag210_to_senseid - convert diag 0x210 data to sense id information
33 * @diag: diag 0x210 data
35 * Return 0 on success, non-zero otherwise.
42 { 0x08, 0x01, 0x3480 }, in diag210_to_senseid()
43 { 0x08, 0x02, 0x3430 }, in diag210_to_senseid()
44 { 0x08, 0x10, 0x3420 }, in diag210_to_senseid()
45 { 0x08, 0x42, 0x3424 }, in diag210_to_senseid()
46 { 0x08, 0x44, 0x9348 }, in diag210_to_senseid()
47 { 0x08, 0x81, 0x3490 }, in diag210_to_senseid()
48 { 0x08, 0x82, 0x3422 }, in diag210_to_senseid()
[all …]
/linux/drivers/net/ethernet/netronome/nfp/nfpcore/
H A Dnfp_dev.h9 #define PCI_VENDOR_ID_CORIGINE 0x1da8
10 #define PCI_DEVICE_ID_NFP3800 0x3800
11 #define PCI_DEVICE_ID_NFP4000 0x4000
12 #define PCI_DEVICE_ID_NFP5000 0x5000
13 #define PCI_DEVICE_ID_NFP6000 0x6000
14 #define PCI_DEVICE_ID_NFP3800_VF 0x3803
15 #define PCI_DEVICE_ID_NFP6000_VF 0x6003
/linux/drivers/net/ethernet/chelsio/cxgb3/
H A Dmc5.c42 DBGI_MODE_MBUS = 0,
47 #define IDT_CMD_READ 0
53 #define IDT_LAR_ADR0 0x180006
54 #define IDT_LAR_MODE144 0xffff0000
57 #define IDT_SCR_ADR0 0x180000
58 #define IDT_SSR0_ADR0 0x180002
59 #define IDT_SSR1_ADR0 0x180004
62 #define IDT_GMR_BASE_ADR0 0x180020
65 #define IDT_DATARY_BASE_ADR0 0
66 #define IDT_MSKARY_BASE_ADR0 0x80000
[all …]
/linux/drivers/media/i2c/
H A Dov13b10.c19 #define OV13B10_REG_MODE_SELECT 0x0100
20 #define OV13B10_MODE_STANDBY 0x00
21 #define OV13B10_MODE_STREAMING 0x01
23 #define OV13B10_REG_SOFTWARE_RST 0x0103
24 #define OV13B10_SOFTWARE_RST 0x01
27 #define OV13B10_REG_CHIP_ID 0x300a
28 #define OV13B10_CHIP_ID 0x560d42
31 #define OV13B10_REG_VTS 0x380e
32 #define OV13B10_VTS_30FPS 0x0c7c
33 #define OV13B10_VTS_60FPS 0x063e
[all …]
H A Dov5695.c30 #define CHIP_ID 0x005695
31 #define OV5695_REG_CHIP_ID 0x300a
33 #define OV5695_REG_CTRL_MODE 0x0100
34 #define OV5695_MODE_SW_STANDBY 0x0
35 #define OV5695_MODE_STREAMING BIT(0)
37 #define OV5695_REG_EXPOSURE 0x3500
40 #define OV5695_VTS_MAX 0x7fff
42 #define OV5695_REG_ANALOG_GAIN 0x3509
43 #define ANALOG_GAIN_MIN 0x10
44 #define ANALOG_GAIN_MAX 0xf8
[all …]
H A Dov5647.c42 #define MIPI_CTRL00_CLOCK_LANE_DISABLE BIT(0)
44 #define OV5647_SW_STANDBY 0x0100
45 #define OV5647_SW_RESET 0x0103
46 #define OV5647_REG_CHIPID_H 0x300a
47 #define OV5647_REG_CHIPID_L 0x300b
48 #define OV5640_REG_PAD_OUT 0x300d
49 #define OV5647_REG_EXP_HI 0x3500
50 #define OV5647_REG_EXP_MID 0x3501
51 #define OV5647_REG_EXP_LO 0x3502
52 #define OV5647_REG_AEC_AGC 0x3503
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_4_1_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2
36 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1
[all …]
/linux/drivers/net/ethernet/apm/xgene/
H A Dxgene_enet_xgmac.h12 #define X2_BLOCK_ETH_MAC_CSR_OFFSET 0x3000
13 #define BLOCK_AXG_MAC_OFFSET 0x0800
14 #define BLOCK_AXG_STATS_OFFSET 0x0800
15 #define BLOCK_AXG_MAC_CSR_OFFSET 0x2000
16 #define BLOCK_PCS_OFFSET 0x3800
18 #define XGENET_CONFIG_REG_ADDR 0x20
19 #define XGENET_SRST_ADDR 0x00
20 #define XGENET_CLKEN_ADDR 0x08
22 #define CSR_CLK BIT(0)
29 #define CSR_RST BIT(0)
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/ce/
H A Dgt215.c36 { 0x0001, "ILLEGAL_MTHD" },
37 { 0x0002, "INVALID_ENUM" },
38 { 0x0003, "INVALID_BITFIELD" },
47 const u32 base = subdev->inst * 0x1000; in gt215_ce_intr()
48 u32 ssta = nvkm_rd32(device, 0x104040 + base) & 0x0000ffff; in gt215_ce_intr()
49 u32 addr = nvkm_rd32(device, 0x104040 + base) >> 16; in gt215_ce_intr()
50 u32 mthd = (addr & 0x07ff) << 2; in gt215_ce_intr()
51 u32 subc = (addr & 0x3800) >> 11; in gt215_ce_intr()
52 u32 data = nvkm_rd32(device, 0x104044 + base); in gt215_ce_intr()
59 chan ? chan->inst->addr : 0, in gt215_ce_intr()
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/sec/
H A Dg98.c35 { 0x0000, "ILLEGAL_MTHD" },
36 { 0x0001, "INVALID_BITFIELD" },
37 { 0x0002, "INVALID_ENUM" },
38 { 0x0003, "QUERY" },
47 u32 ssta = nvkm_rd32(device, 0x087040) & 0x0000ffff; in g98_sec_intr()
48 u32 addr = nvkm_rd32(device, 0x087040) >> 16; in g98_sec_intr()
49 u32 mthd = (addr & 0x07ff) << 2; in g98_sec_intr()
50 u32 subc = (addr & 0x3800) >> 11; in g98_sec_intr()
51 u32 data = nvkm_rd32(device, 0x087044); in g98_sec_intr()
58 chan ? chan->inst->addr : 0, in g98_sec_intr()
[all …]
/linux/drivers/net/wireless/broadcom/brcm80211/include/
H A Dbrcmu_d11.h20 /* bit 0~7 channel number
21 * for 80+80 channels: bit 0~3 low channel id, bit 4~7 high channel id
23 #define BRCMU_CHSPEC_CH_MASK 0x00ff
24 #define BRCMU_CHSPEC_CH_SHIFT 0
25 #define BRCMU_CHSPEC_CHL_MASK 0x000f
26 #define BRCMU_CHSPEC_CHL_SHIFT 0
27 #define BRCMU_CHSPEC_CHH_MASK 0x00f0
36 #define BRCMU_CHSPEC_D11N_SB_MASK 0x0300
38 #define BRCMU_CHSPEC_D11N_SB_L 0x0100 /* control lower */
39 #define BRCMU_CHSPEC_D11N_SB_U 0x0200 /* control upper */
[all …]
/linux/arch/x86/math-emu/
H A Dstatus_w.h22 #define SW_Backward Const__(0x8000) /* backward compatibility */
23 #define SW_C3 Const__(0x4000) /* condition bit 3 */
24 #define SW_Top Const__(0x3800) /* top of stack */
26 #define SW_C2 Const__(0x0400) /* condition bit 2 */
27 #define SW_C1 Const__(0x0200) /* condition bit 1 */
28 #define SW_C0 Const__(0x0100) /* condition bit 0 */
29 #define SW_Summary Const__(0x0080) /* exception summary */
30 #define SW_Stack_Fault Const__(0x0040) /* stack fault */
31 #define SW_Precision Const__(0x0020) /* loss of precision */
32 #define SW_Underflow Const__(0x0010) /* underflow */
[all …]
/linux/arch/m68k/ifpsp060/src/
H A Dilsp.S36 short 0x0000
38 short 0x0000
41 short 0x0000
43 short 0x0000
46 short 0x0000
48 short 0x0000
50 short 0x0000
52 short 0x0000
54 short 0x0000
56 short 0x0000
[all …]
/linux/sound/soc/codecs/
H A Drt700.h30 #define RT700_AUDIO_FUNCTION_GROUP 0x01
31 #define RT700_DAC_OUT1 0x02
32 #define RT700_DAC_OUT2 0x03
33 #define RT700_ADC_IN1 0x09
34 #define RT700_ADC_IN2 0x08
35 #define RT700_DMIC1 0x12
36 #define RT700_DMIC2 0x13
37 #define RT700_SPK_OUT 0x14
38 #define RT700_MIC2 0x19
39 #define RT700_LINE1 0x1a
[all …]
H A Drt715.h30 #define RT715_AUDIO_FUNCTION_GROUP 0x01
31 #define RT715_MIC_ADC 0x07
32 #define RT715_LINE_ADC 0x08
33 #define RT715_MIX_ADC 0x09
34 #define RT715_DMIC1 0x12
35 #define RT715_DMIC2 0x13
36 #define RT715_MIC1 0x18
37 #define RT715_MIC2 0x19
38 #define RT715_LINE1 0x1a
39 #define RT715_LINE2 0x1b
[all …]
H A Drt711.h32 #define RT711_AUDIO_FUNCTION_GROUP 0x01
33 #define RT711_DAC_OUT2 0x03
34 #define RT711_ADC_IN1 0x09
35 #define RT711_ADC_IN2 0x08
36 #define RT711_DMIC1 0x12
37 #define RT711_DMIC2 0x13
38 #define RT711_MIC2 0x19
39 #define RT711_LINE1 0x1a
40 #define RT711_LINE2 0x1b
41 #define RT711_BEEP 0x1d
[all …]
/linux/drivers/gpu/drm/amd/display/dc/spl/
H A Ddc_spl_scl_easf_filters.c22 0x0200, 0x0200, 0x0000,
23 0x01F6, 0x0206, 0x0004,
24 0x01EC, 0x020B, 0x0009,
25 0x01E2, 0x0211, 0x000D,
26 0x01D8, 0x0216, 0x0012,
27 0x01CE, 0x021C, 0x0016,
28 0x01C4, 0x0221, 0x001B,
29 0x01BA, 0x0226, 0x0020,
30 0x01B0, 0x022A, 0x0026,
31 0x01A6, 0x022F, 0x002B,
[all …]
/linux/drivers/media/tuners/
H A Dmc44s803_priv.h14 SPI or I2C Address : 0xc0-0xc6
28 0A | LNA AGC
29 0B | Data Register Address
30 0C | Regulator Test
31 0D | VCO Test
32 0E | LNA Gain/Input Power
33 0F | ID Bits
41 #define MC44S803_REG_POWER 0
51 #define MC44S803_REG_LNAAGC 0x0A
52 #define MC44S803_REG_DATAREG 0x0B
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,xsphy.yaml20 u2 port0 0x0000 MISC
21 0x0100 FMREG
22 0x0300 U2PHY_COM
23 u2 port1 0x1000 MISC
24 0x1100 FMREG
25 0x1300 U2PHY_COM
26 u2 port2 0x2000 MISC
28 u31 common 0x3000 DIG_GLB
29 0x3100 PHYA_GLB
30 u31 port0 0x3400 DIG_LN_TOP
[all …]
/linux/lib/
H A Dbitfield_kunit.c17 "u" #tp "_encode_bits(" #v ", " #field ") is 0x%llx != " #res "\n", \
22 } while (0)
31 "le" #tp "_encode_bits(" #v ", " #field ") is 0x%llx != 0x%llx",\
37 } while (0)
46 "be" #tp "_encode_bits(" #v ", " #field ") is 0x%llx != 0x%llx", \
52 } while (0)
58 } while (0)
68 CHECK_ENC_GET(16, 1, 0x000f, 0x0001); in test_bitfields_constants()
69 CHECK_ENC_GET(16, 3, 0x00f0, 0x0030); in test_bitfields_constants()
70 CHECK_ENC_GET(16, 5, 0x0f00, 0x0500); in test_bitfields_constants()
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb4/
H A Dcudbg_entity.h9 #define EDC0_FLAG 0
16 #define CUDBG_ENTITY_SIGNATURE 0xCCEDB001
98 /* Memory region info relative to current memory (i.e. wrt 0). */
101 u32 start; /* Start wrt 0 */
102 u32 end; /* End wrt 0 */
223 #define CUDBG_VPD_VER_ADDR 0x18c7
239 #define CUDBG_MAX_TCAM_TID 0x800
245 LE_ET_UNKNOWN = 0,
288 #define CUDBG_CHAC_PBT_ADDR 0x2800
289 #define CUDBG_CHAC_PBT_LRF 0x3000
[all …]
/linux/sound/pci/cs46xx/
H A Dcs46xx_lib.h14 #define CS46XX_BA0_SIZE 0x1000
15 #define CS46XX_BA1_DATA0_SIZE 0x3000
16 #define CS46XX_BA1_DATA1_SIZE 0x3800
17 #define CS46XX_BA1_PRG_SIZE 0x7000
18 #define CS46XX_BA1_REG_SIZE 0x0100
33 #define SCB_NO_PARENT 0
48 unsigned int offset = reg & 0xffff; in snd_cs46xx_poke()
51 if (bank == 0) in snd_cs46xx_poke()
61 unsigned int offset = reg & 0xffff; in snd_cs46xx_peek()
/linux/drivers/net/ethernet/asix/
H A Dax88796c_main.h26 #define AX88796C_PHY_ID 0x10
34 #define TX_HDR_SOP_DICF 0x8000
35 #define TX_HDR_SOP_CPHI 0x4000
36 #define TX_HDR_SOP_INT 0x2000
37 #define TX_HDR_SOP_MDEQ 0x1000
38 #define TX_HDR_SOP_PKTLEN 0x07FF
39 #define TX_HDR_SOP_SEQNUM 0xF800
40 #define TX_HDR_SOP_PKTLENBAR 0x07FF
42 #define TX_HDR_SEG_FS 0x8000
43 #define TX_HDR_SEG_LS 0x4000
[all …]
/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Dpsoc_etr_masks.h24 #define PSOC_ETR_RSZ_RSZ_ETR_SHIFT 0
25 #define PSOC_ETR_RSZ_RSZ_ETR_MASK 0x7FFFFFFF
28 #define PSOC_ETR_STS_FULL_SHIFT 0
29 #define PSOC_ETR_STS_FULL_MASK 0x1
31 #define PSOC_ETR_STS_TRIGGERED_MASK 0x2
33 #define PSOC_ETR_STS_TMCREADY_MASK 0x4
35 #define PSOC_ETR_STS_FTEMPTY_MASK 0x8
37 #define PSOC_ETR_STS_EMPTY_MASK 0x10
39 #define PSOC_ETR_STS_MEMERR_MASK 0x20
42 #define PSOC_ETR_RRD_RRD_SHIFT 0
[all …]

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