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/linux/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A Dgaudi_blocks.h16 #define mmNIC0_PHY0_BASE 0x0ull
17 #define NIC0_PHY0_MAX_OFFSET 0x9F13
18 #define mmMME0_ACC_BASE 0x7FFC020000ull
19 #define MME0_ACC_MAX_OFFSET 0x5C00
20 #define MME0_ACC_SECTION 0x20000
21 #define mmMME0_SBAB_BASE 0x7FFC040000ull
22 #define MME0_SBAB_MAX_OFFSET 0x5800
23 #define MME0_SBAB_SECTION 0x1000
24 #define mmMME0_PRTN_BASE 0x7FFC041000ull
25 #define MME0_PRTN_MAX_OFFSET 0x5000
[all …]
/linux/drivers/net/ethernet/netronome/nfp/nfpcore/
H A Dnfp_dev.h9 #define PCI_VENDOR_ID_CORIGINE 0x1da8
10 #define PCI_DEVICE_ID_NFP3800 0x3800
11 #define PCI_DEVICE_ID_NFP4000 0x4000
12 #define PCI_DEVICE_ID_NFP5000 0x5000
13 #define PCI_DEVICE_ID_NFP6000 0x6000
14 #define PCI_DEVICE_ID_NFP3800_VF 0x3803
15 #define PCI_DEVICE_ID_NFP6000_VF 0x6003
/linux/drivers/net/ethernet/chelsio/cxgb3/
H A Dmc5.c42 DBGI_MODE_MBUS = 0,
47 #define IDT_CMD_READ 0
53 #define IDT_LAR_ADR0 0x180006
54 #define IDT_LAR_MODE144 0xffff0000
57 #define IDT_SCR_ADR0 0x180000
58 #define IDT_SSR0_ADR0 0x180002
59 #define IDT_SSR1_ADR0 0x180004
62 #define IDT_GMR_BASE_ADR0 0x180020
65 #define IDT_DATARY_BASE_ADR0 0
66 #define IDT_MSKARY_BASE_ADR0 0x80000
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_4_1_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2
36 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1
[all …]
/linux/drivers/net/ethernet/apm/xgene/
H A Dxgene_enet_xgmac.h12 #define X2_BLOCK_ETH_MAC_CSR_OFFSET 0x3000
13 #define BLOCK_AXG_MAC_OFFSET 0x0800
14 #define BLOCK_AXG_STATS_OFFSET 0x0800
15 #define BLOCK_AXG_MAC_CSR_OFFSET 0x2000
16 #define BLOCK_PCS_OFFSET 0x3800
18 #define XGENET_CONFIG_REG_ADDR 0x20
19 #define XGENET_SRST_ADDR 0x00
20 #define XGENET_CLKEN_ADDR 0x08
22 #define CSR_CLK BIT(0)
29 #define CSR_RST BIT(0)
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/ce/
H A Dgt215.c36 { 0x0001, "ILLEGAL_MTHD" },
37 { 0x0002, "INVALID_ENUM" },
38 { 0x0003, "INVALID_BITFIELD" },
47 const u32 base = subdev->inst * 0x1000; in gt215_ce_intr()
48 u32 ssta = nvkm_rd32(device, 0x104040 + base) & 0x0000ffff; in gt215_ce_intr()
49 u32 addr = nvkm_rd32(device, 0x104040 + base) >> 16; in gt215_ce_intr()
50 u32 mthd = (addr & 0x07ff) << 2; in gt215_ce_intr()
51 u32 subc = (addr & 0x3800) >> 11; in gt215_ce_intr()
52 u32 data = nvkm_rd32(device, 0x104044 + base); in gt215_ce_intr()
59 chan ? chan->inst->addr : 0, in gt215_ce_intr()
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/sec/
H A Dg98.c35 { 0x0000, "ILLEGAL_MTHD" },
36 { 0x0001, "INVALID_BITFIELD" },
37 { 0x0002, "INVALID_ENUM" },
38 { 0x0003, "QUERY" },
47 u32 ssta = nvkm_rd32(device, 0x087040) & 0x0000ffff; in g98_sec_intr()
48 u32 addr = nvkm_rd32(device, 0x087040) >> 16; in g98_sec_intr()
49 u32 mthd = (addr & 0x07ff) << 2; in g98_sec_intr()
50 u32 subc = (addr & 0x3800) >> 11; in g98_sec_intr()
51 u32 data = nvkm_rd32(device, 0x087044); in g98_sec_intr()
58 chan ? chan->inst->addr : 0, in g98_sec_intr()
[all …]
/linux/drivers/net/wireless/broadcom/brcm80211/include/
H A Dbrcmu_d11.h20 /* bit 0~7 channel number
21 * for 80+80 channels: bit 0~3 low channel id, bit 4~7 high channel id
23 #define BRCMU_CHSPEC_CH_MASK 0x00ff
24 #define BRCMU_CHSPEC_CH_SHIFT 0
25 #define BRCMU_CHSPEC_CHL_MASK 0x000f
26 #define BRCMU_CHSPEC_CHL_SHIFT 0
27 #define BRCMU_CHSPEC_CHH_MASK 0x00f0
36 #define BRCMU_CHSPEC_D11N_SB_MASK 0x0300
38 #define BRCMU_CHSPEC_D11N_SB_L 0x0100 /* control lower */
39 #define BRCMU_CHSPEC_D11N_SB_U 0x0200 /* control upper */
[all …]
/linux/arch/m68k/ifpsp060/src/
H A Dilsp.S36 short 0x0000
38 short 0x0000
41 short 0x0000
43 short 0x0000
46 short 0x0000
48 short 0x0000
50 short 0x0000
52 short 0x0000
54 short 0x0000
56 short 0x0000
[all …]
/linux/sound/soc/codecs/
H A Drt700.h30 #define RT700_AUDIO_FUNCTION_GROUP 0x01
31 #define RT700_DAC_OUT1 0x02
32 #define RT700_DAC_OUT2 0x03
33 #define RT700_ADC_IN1 0x09
34 #define RT700_ADC_IN2 0x08
35 #define RT700_DMIC1 0x12
36 #define RT700_DMIC2 0x13
37 #define RT700_SPK_OUT 0x14
38 #define RT700_MIC2 0x19
39 #define RT700_LINE1 0x1a
[all …]
H A Drt711.h32 #define RT711_AUDIO_FUNCTION_GROUP 0x01
33 #define RT711_DAC_OUT2 0x03
34 #define RT711_ADC_IN1 0x09
35 #define RT711_ADC_IN2 0x08
36 #define RT711_DMIC1 0x12
37 #define RT711_DMIC2 0x13
38 #define RT711_MIC2 0x19
39 #define RT711_LINE1 0x1a
40 #define RT711_LINE2 0x1b
41 #define RT711_BEEP 0x1d
[all …]
H A Dad1980.c31 { 0x02, 0x8000 },
32 { 0x04, 0x8000 },
33 { 0x06, 0x8000 },
34 { 0x0c, 0x8008 },
35 { 0x0e, 0x8008 },
36 { 0x10, 0x8808 },
37 { 0x12, 0x8808 },
38 { 0x16, 0x8808 },
39 { 0x18, 0x8808 },
40 { 0x1a, 0x0000 },
[all …]
/linux/drivers/media/tuners/
H A Dmc44s803_priv.h14 SPI or I2C Address : 0xc0-0xc6
28 0A | LNA AGC
29 0B | Data Register Address
30 0C | Regulator Test
31 0D | VCO Test
32 0E | LNA Gain/Input Power
33 0F | ID Bits
41 #define MC44S803_REG_POWER 0
51 #define MC44S803_REG_LNAAGC 0x0A
52 #define MC44S803_REG_DATAREG 0x0B
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,xsphy.yaml20 u2 port0 0x0000 MISC
21 0x0100 FMREG
22 0x0300 U2PHY_COM
23 u2 port1 0x1000 MISC
24 0x1100 FMREG
25 0x1300 U2PHY_COM
26 u2 port2 0x2000 MISC
28 u31 common 0x3000 DIG_GLB
29 0x3100 PHYA_GLB
30 u31 port0 0x3400 DIG_LN_TOP
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb4/
H A Dcudbg_entity.h9 #define EDC0_FLAG 0
16 #define CUDBG_ENTITY_SIGNATURE 0xCCEDB001
98 /* Memory region info relative to current memory (i.e. wrt 0). */
101 u32 start; /* Start wrt 0 */
102 u32 end; /* End wrt 0 */
223 #define CUDBG_VPD_VER_ADDR 0x18c7
239 #define CUDBG_MAX_TCAM_TID 0x800
245 LE_ET_UNKNOWN = 0,
288 #define CUDBG_CHAC_PBT_ADDR 0x2800
289 #define CUDBG_CHAC_PBT_LRF 0x3000
[all …]
/linux/sound/pci/cs46xx/
H A Dcs46xx_lib.h14 #define CS46XX_BA0_SIZE 0x1000
15 #define CS46XX_BA1_DATA0_SIZE 0x3000
16 #define CS46XX_BA1_DATA1_SIZE 0x3800
17 #define CS46XX_BA1_PRG_SIZE 0x7000
18 #define CS46XX_BA1_REG_SIZE 0x0100
33 #define SCB_NO_PARENT 0
48 unsigned int offset = reg & 0xffff; in snd_cs46xx_poke()
51 if (bank == 0) in snd_cs46xx_poke()
61 unsigned int offset = reg & 0xffff; in snd_cs46xx_peek()
/linux/drivers/net/ethernet/asix/
H A Dax88796c_main.h26 #define AX88796C_PHY_ID 0x10
34 #define TX_HDR_SOP_DICF 0x8000
35 #define TX_HDR_SOP_CPHI 0x4000
36 #define TX_HDR_SOP_INT 0x2000
37 #define TX_HDR_SOP_MDEQ 0x1000
38 #define TX_HDR_SOP_PKTLEN 0x07FF
39 #define TX_HDR_SOP_SEQNUM 0xF800
40 #define TX_HDR_SOP_PKTLENBAR 0x07FF
42 #define TX_HDR_SEG_FS 0x8000
43 #define TX_HDR_SEG_LS 0x4000
[all …]
/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Dpsoc_etr_masks.h24 #define PSOC_ETR_RSZ_RSZ_ETR_SHIFT 0
25 #define PSOC_ETR_RSZ_RSZ_ETR_MASK 0x7FFFFFFF
28 #define PSOC_ETR_STS_FULL_SHIFT 0
29 #define PSOC_ETR_STS_FULL_MASK 0x1
31 #define PSOC_ETR_STS_TRIGGERED_MASK 0x2
33 #define PSOC_ETR_STS_TMCREADY_MASK 0x4
35 #define PSOC_ETR_STS_FTEMPTY_MASK 0x8
37 #define PSOC_ETR_STS_EMPTY_MASK 0x10
39 #define PSOC_ETR_STS_MEMERR_MASK 0x20
42 #define PSOC_ETR_RRD_RRD_SHIFT 0
[all …]
/linux/drivers/scsi/qla4xxx/
H A Dql4_83xx.h11 #define QLA83XX_FLASH_SPI_STATUS 0x2808E010
12 #define QLA83XX_FLASH_SPI_CONTROL 0x2808E014
13 #define QLA83XX_FLASH_STATUS 0x42100004
14 #define QLA83XX_FLASH_CONTROL 0x42110004
15 #define QLA83XX_FLASH_ADDR 0x42110008
16 #define QLA83XX_FLASH_WRDATA 0x4211000C
17 #define QLA83XX_FLASH_RDDATA 0x42110018
18 #define QLA83XX_FLASH_DIRECT_WINDOW 0x42110030
19 #define QLA83XX_FLASH_DIRECT_DATA(DATA) (0x42150000 | (0x0000FFFF&DATA))
24 #define QLA83XX_FLASH_LOCK 0x3850
[all …]
/linux/arch/x86/pci/
H A Dcommon.c31 int noioapicreroute = 0;
43 if (domain == 0 && reg < 256 && raw_pci_ops) in raw_pci_read()
53 if (domain == 0 && reg < 256 && raw_pci_ops) in raw_pci_write()
87 return 0; in can_skip_ioresource_align()
97 .ident = "IBM System x3800",
100 DMI_MATCH(DMI_PRODUCT_NAME, "x3800"),
139 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) { in pcibios_fixup_device_resources()
141 if (bar_r->start == 0 && bar_r->end != 0) { in pcibios_fixup_device_resources()
142 bar_r->flags = 0; in pcibios_fixup_device_resources()
143 bar_r->end = 0; in pcibios_fixup_device_resources()
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
H A Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
H A Dgfx_8_1_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
/linux/drivers/net/wireless/intel/iwlegacy/
H A Dprph.h70 #define PRPH_BASE (0x00000)
71 #define PRPH_END (0xFFFFF)
74 #define APMG_BASE (PRPH_BASE + 0x3000)
75 #define APMG_CLK_CTRL_REG (APMG_BASE + 0x0000)
76 #define APMG_CLK_EN_REG (APMG_BASE + 0x0004)
77 #define APMG_CLK_DIS_REG (APMG_BASE + 0x0008)
78 #define APMG_PS_CTRL_REG (APMG_BASE + 0x000c)
79 #define APMG_PCIDEV_STT_REG (APMG_BASE + 0x0010)
80 #define APMG_RFKILL_REG (APMG_BASE + 0x0014)
81 #define APMG_RTC_INT_STT_REG (APMG_BASE + 0x001c)
[all …]
/linux/arch/arm64/boot/dts/synaptics/
H A Dberlin4ct.dtsi27 #size-cells = <0>;
29 cpu0: cpu@0 {
32 reg = <0x0>;
41 reg = <0x1>;
50 reg = <0x2>;
59 reg = <0x3>;
73 CPU_SLEEP_0: cpu-sleep-0 {
76 arm,psci-suspend-param = <0x0010000>;
86 #clock-cells = <0>;
114 ranges = <0 0 0xf7000000 0x1000000>;
[all …]

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