1*1ccea77eSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 20148d38dSIyappan Subramanian /* Applied Micro X-Gene SoC Ethernet Driver 30148d38dSIyappan Subramanian * 40148d38dSIyappan Subramanian * Copyright (c) 2014, Applied Micro Circuits Corporation 50148d38dSIyappan Subramanian * Authors: Iyappan Subramanian <isubramanian@apm.com> 60148d38dSIyappan Subramanian * Keyur Chudgar <kchudgar@apm.com> 70148d38dSIyappan Subramanian */ 80148d38dSIyappan Subramanian 90148d38dSIyappan Subramanian #ifndef __XGENE_ENET_XGMAC_H__ 100148d38dSIyappan Subramanian #define __XGENE_ENET_XGMAC_H__ 110148d38dSIyappan Subramanian 12561fea6dSIyappan Subramanian #define X2_BLOCK_ETH_MAC_CSR_OFFSET 0x3000 130148d38dSIyappan Subramanian #define BLOCK_AXG_MAC_OFFSET 0x0800 142d07d8e4SQuan Nguyen #define BLOCK_AXG_STATS_OFFSET 0x0800 150148d38dSIyappan Subramanian #define BLOCK_AXG_MAC_CSR_OFFSET 0x2000 163eb7cb9dSIyappan Subramanian #define BLOCK_PCS_OFFSET 0x3800 170148d38dSIyappan Subramanian 18561fea6dSIyappan Subramanian #define XGENET_CONFIG_REG_ADDR 0x20 19561fea6dSIyappan Subramanian #define XGENET_SRST_ADDR 0x00 20561fea6dSIyappan Subramanian #define XGENET_CLKEN_ADDR 0x08 21bc1b7c13SIyappan Subramanian 22bc1b7c13SIyappan Subramanian #define CSR_CLK BIT(0) 23bc1b7c13SIyappan Subramanian #define XGENET_CLK BIT(1) 24bc1b7c13SIyappan Subramanian #define PCS_CLK BIT(3) 25bc1b7c13SIyappan Subramanian #define AN_REF_CLK BIT(4) 26bc1b7c13SIyappan Subramanian #define AN_CLK BIT(5) 27bc1b7c13SIyappan Subramanian #define AD_CLK BIT(6) 28bc1b7c13SIyappan Subramanian 29bc1b7c13SIyappan Subramanian #define CSR_RST BIT(0) 30bc1b7c13SIyappan Subramanian #define XGENET_RST BIT(1) 31bc1b7c13SIyappan Subramanian #define PCS_RST BIT(3) 32bc1b7c13SIyappan Subramanian #define AN_REF_RST BIT(4) 33bc1b7c13SIyappan Subramanian #define AN_RST BIT(5) 34bc1b7c13SIyappan Subramanian #define AD_RST BIT(6) 35bc1b7c13SIyappan Subramanian 360148d38dSIyappan Subramanian #define AXGMAC_CONFIG_0 0x0000 370148d38dSIyappan Subramanian #define AXGMAC_CONFIG_1 0x0004 380148d38dSIyappan Subramanian #define HSTMACRST BIT(31) 390148d38dSIyappan Subramanian #define HSTTCTLEN BIT(31) 400148d38dSIyappan Subramanian #define HSTTFEN BIT(30) 410148d38dSIyappan Subramanian #define HSTRCTLEN BIT(29) 420148d38dSIyappan Subramanian #define HSTRFEN BIT(28) 430148d38dSIyappan Subramanian #define HSTPPEN BIT(7) 440148d38dSIyappan Subramanian #define HSTDRPLT64 BIT(5) 450148d38dSIyappan Subramanian #define HSTLENCHK BIT(3) 460148d38dSIyappan Subramanian #define HSTMACADR_LSW_ADDR 0x0010 470148d38dSIyappan Subramanian #define HSTMACADR_MSW_ADDR 0x0014 480148d38dSIyappan Subramanian #define HSTMAXFRAME_LENGTH_ADDR 0x0020 490148d38dSIyappan Subramanian 50561fea6dSIyappan Subramanian #define XG_MCX_RX_DV_GATE_REG_0_ADDR 0x0004 51bb64fa09SIyappan Subramanian #define XG_MCX_ECM_CFG_0_ADDR 0x0074 5256090b12SIyappan Subramanian #define XG_MCX_MULTI_DPF0_ADDR 0x007c 5356090b12SIyappan Subramanian #define XG_MCX_MULTI_DPF1_ADDR 0x0080 5456090b12SIyappan Subramanian #define XG_DEF_PAUSE_THRES 0x390 5556090b12SIyappan Subramanian #define XG_DEF_PAUSE_OFF_THRES 0x2c0 560148d38dSIyappan Subramanian #define XG_RSIF_CONFIG_REG_ADDR 0x00a0 577eac928cSQuan Nguyen #define XG_RSIF_CLE_BUFF_THRESH 0x3 587eac928cSQuan Nguyen #define RSIF_CLE_BUFF_THRESH_SET(dst, val) xgene_set_bits(dst, val, 0, 3) 597eac928cSQuan Nguyen #define XG_RSIF_CONFIG1_REG_ADDR 0x00b8 607eac928cSQuan Nguyen #define XG_RSIF_PLC_CLE_BUFF_THRESH 0x1 617eac928cSQuan Nguyen #define RSIF_PLC_CLE_BUFF_THRESH_SET(dst, val) xgene_set_bits(dst, val, 0, 2) 62ca6d550cSIyappan Subramanian #define XG_MCX_ECM_CONFIG0_REG_0_ADDR 0x0070 63ca6d550cSIyappan Subramanian #define XG_MCX_ICM_ECM_DROP_COUNT_REG0_ADDR 0x0124 640148d38dSIyappan Subramanian #define XCLE_BYPASS_REG0_ADDR 0x0160 650148d38dSIyappan Subramanian #define XCLE_BYPASS_REG1_ADDR 0x0164 660148d38dSIyappan Subramanian #define XG_CFG_BYPASS_ADDR 0x0204 679b00eb49SIyappan Subramanian #define XG_CFG_LINK_AGGR_RESUME_0_ADDR 0x0214 680148d38dSIyappan Subramanian #define XG_LINK_STATUS_ADDR 0x0228 699b00eb49SIyappan Subramanian #define XG_TSIF_MSS_REG0_ADDR 0x02a4 709a8c5ddeSIyappan Subramanian #define XG_DEBUG_REG_ADDR 0x0400 710148d38dSIyappan Subramanian #define XG_ENET_SPARE_CFG_REG_ADDR 0x040c 720148d38dSIyappan Subramanian #define XG_ENET_SPARE_CFG_REG_1_ADDR 0x0410 730148d38dSIyappan Subramanian #define XGENET_RX_DV_GATE_REG_0_ADDR 0x0804 74ca6d550cSIyappan Subramanian #define XGENET_ECM_CONFIG0_REG_0 0x0870 75ca6d550cSIyappan Subramanian #define XGENET_ICM_ECM_DROP_COUNT_REG0 0x0924 76bb64fa09SIyappan Subramanian #define XGENET_CSR_ECM_CFG_0_ADDR 0x0880 7756090b12SIyappan Subramanian #define XGENET_CSR_MULTI_DPF0_ADDR 0x0888 7856090b12SIyappan Subramanian #define XGENET_CSR_MULTI_DPF1_ADDR 0x088c 7956090b12SIyappan Subramanian #define XG_RXBUF_PAUSE_THRESH 0x0020 809a8c5ddeSIyappan Subramanian #define XG_MCX_ICM_CONFIG0_REG_0_ADDR 0x00e0 819a8c5ddeSIyappan Subramanian #define XG_MCX_ICM_CONFIG2_REG_0_ADDR 0x00e8 820148d38dSIyappan Subramanian 833eb7cb9dSIyappan Subramanian #define PCS_CONTROL_1 0x0000 843eb7cb9dSIyappan Subramanian #define PCS_CTRL_PCS_RST BIT(15) 853eb7cb9dSIyappan Subramanian 863cdb7309SJulia Lawall extern const struct xgene_mac_ops xgene_xgmac_ops; 873cdb7309SJulia Lawall extern const struct xgene_port_ops xgene_xgport_ops; 880148d38dSIyappan Subramanian 890148d38dSIyappan Subramanian #endif /* __XGENE_ENET_XGMAC_H__ */ 90