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/linux/drivers/video/fbdev/
H A Dplatinumfb.h54 * F = 14.3MHz * c0 / (c1 & 0x1f) / (1 << (c1 >> 5))
55 * Newer ones use the values in clocksel[0], for which the formula
57 * F = 15MHz * c0 / ((c1 & 0x1f) + 2) / (1 << (c1 >> 5))
69 #define DIV2 0x20
70 #define DIV4 0x40
71 #define DIV8 0x60
72 #define DIV16 0x80
76 0x5c00,
78 { 0xffc, 4, 0, 0, 0, 0, 0x428, 0,
79 0, 0xb3, 0xd3, 0x12, 0x1a5, 0x23, 0x28, 0x2d,
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mt8192.c27 FACTOR_FLAGS(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3, 0),
28 FACTOR_FLAGS(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4, 0),
29 FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2, 0),
30 FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4, 0),
31 FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8, 0),
32 FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D16, "mainpll_d4_d16", "mainpll_d4", 1, 16, 0),
33 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5, 0),
34 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2, 0),
35 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4, 0),
36 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8, 0),
[all …]
H A Dclk-mt8183.c35 FACTOR_FLAGS(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, 1, 0),
36 FACTOR_FLAGS(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1, 2, 0),
37 FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D2, "syspll_d2_d2", "syspll_d2", 1, 2, 0),
38 FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D4, "syspll_d2_d4", "syspll_d2", 1, 4, 0),
39 FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D8, "syspll_d2_d8", "syspll_d2", 1, 8, 0),
40 FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D16, "syspll_d2_d16", "syspll_d2", 1, 16, 0),
41 FACTOR_FLAGS(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3, 0),
42 FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D2, "syspll_d3_d2", "syspll_d3", 1, 2, 0),
43 FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D4, "syspll_d3_d4", "syspll_d3", 1, 4, 0),
44 FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D8, "syspll_d3_d8", "syspll_d3", 1, 8, 0),
[all …]
H A Dclk-mt6779.c640 0x20, 0x24, 0x28, 0, 2, 7,
641 0x004, 0, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
643 0x20, 0x24, 0x28, 8, 3, 15, 0x004, 1),
645 0x20, 0x24, 0x28, 16, 3, 23, 0x004, 2),
648 0x30, 0x34, 0x38, 0, 3, 7, 0x004, 4),
650 0x30, 0x34, 0x38, 8, 3, 15, 0x004, 5),
652 0x30, 0x34, 0x38, 16, 3, 23, 0x004, 6),
654 0x30, 0x34, 0x38, 24, 4, 31, 0x004, 7),
657 0x40, 0x44, 0x48, 0, 4, 7, 0x004, 8),
659 0x40, 0x44, 0x48, 8, 4, 15, 0x004, 9),
[all …]
/linux/include/dt-bindings/clock/
H A Dam4.h8 #define AM4_CLKCTRL_OFFSET 0x20
12 #define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120
14 #define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120)
17 #define AM4_L4_WKUP_AON_CLKCTRL_OFFSET 0x228
19 #define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228)
20 #define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230)
23 #define AM4_L4_WKUP_CLKCTRL_OFFSET 0x220
25 #define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220)
26 #define AM4_L4_WKUP_TIMER1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x328)
27 #define AM4_L4_WKUP_WD_TIMER2_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x338)
[all …]
/linux/arch/sh/include/mach-common/mach/
H A Dlboxre2.h12 #define IRQ_CF1 evt2irq(0x320) /* CF1 */
13 #define IRQ_CF0 evt2irq(0x340) /* CF0 */
14 #define IRQ_INTD evt2irq(0x360) /* INTD */
15 #define IRQ_ETH1 evt2irq(0x380) /* Ether1 */
16 #define IRQ_ETH0 evt2irq(0x3a0) /* Ether0 */
17 #define IRQ_INTA evt2irq(0x3c0) /* INTA */
/linux/drivers/memory/tegra/
H A Dtegra210-mc.h12 #define MC_LATENCY_ALLOWANCE_AVPC_0 0x2e4
13 #define MC_LATENCY_ALLOWANCE_HC_0 0x310
14 #define MC_LATENCY_ALLOWANCE_HC_1 0x314
15 #define MC_LATENCY_ALLOWANCE_MPCORE_0 0x320
16 #define MC_LATENCY_ALLOWANCE_NVENC_0 0x328
17 #define MC_LATENCY_ALLOWANCE_PPCS_0 0x344
18 #define MC_LATENCY_ALLOWANCE_PPCS_1 0x348
19 #define MC_LATENCY_ALLOWANCE_ISP2_0 0x370
20 #define MC_LATENCY_ALLOWANCE_ISP2_1 0x374
21 #define MC_LATENCY_ALLOWANCE_XUSB_0 0x37c
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Drockchip-usb-phy.yaml7 title: Rockchip USB2.0 phy
23 const: 0
33 "usb-phy@[0-9a-f]+$":
41 const: 0
50 const: 0
72 #size-cells = <0>;
75 reg = <0x320>;
76 #phy-cells = <0>;
/linux/Documentation/devicetree/bindings/display/panel/
H A Dsamsung,amoled-mipi-dsi.yaml29 # Samsung S6E63J0X03 1.63" 320x320 AMOLED panel
64 #size-cells = <0>;
66 panel@0 {
68 reg = <0>;
71 reset-gpios = <&gpg0 0 GPIO_ACTIVE_LOW>;
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dctxgp104.c29 .bundle_size = 0x3000,
30 .bundle_min_gpm_fifo_depth = 0x180,
31 .bundle_token_limit = 0x900,
33 .pagepool_size = 0x20000,
37 .attrib_nr_max = 0x4b0,
38 .attrib_nr = 0x320,
39 .alpha_nr_max = 0xc00,
40 .alpha_nr = 0x800,
41 .gfxp_nr = 0xba8,
/linux/arch/sh/boards/
H A Dboard-edosk7705.c21 #define SMC_IOBASE 0xA2000000
22 #define SMC_IO_OFFSET 0x300
25 #define ETHERNET_IRQ evt2irq(0x320)
38 [0] = {
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
H A Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
H A Dimxrt1170-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
[all …]
H A Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
/linux/arch/sh/include/mach-landisk/mach/
H A Diodata_landisk.h16 #define PA_USB 0xa4000000 /* USB Controller M66590 */
18 #define PA_ATARST 0xb0000000 /* ATA/FATA Access Control Register */
19 #define PA_LED 0xb0000001 /* LED Control Register */
20 #define PA_STATUS 0xb0000002 /* Switch Status Register */
21 #define PA_SHUTDOWN 0xb0000003 /* Shutdown Control Register */
22 #define PA_PCIPME 0xb0000004 /* PCI PME Status Register */
23 #define PA_IMASK 0xb0000005 /* Interrupt Mask Register */
25 #define PA_PWRINT_CLR 0xb0000006 /* Shutdown Interrupt clear Register */
27 #define PA_PIDE_OFFSET 0x40 /* CF IDE Offset */
28 #define PA_SIDE_OFFSET 0x40 /* HDD IDE Offset */
[all …]
/linux/include/linux/bcma/
H A Dbcma_driver_gmac_cmn.h7 #define BCMA_GMAC_CMN_STAG0 0x000
8 #define BCMA_GMAC_CMN_STAG1 0x004
9 #define BCMA_GMAC_CMN_STAG2 0x008
10 #define BCMA_GMAC_CMN_STAG3 0x00C
11 #define BCMA_GMAC_CMN_PARSER_CTL 0x020
12 #define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
13 #define BCMA_GMAC_CMN_PHY_ACCESS 0x100
14 #define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
15 #define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
17 #define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
/linux/sound/isa/
H A Dcmi8328.c35 static const int cmi8328_ports[] = { 0x530, 0xe80, 0xf40, 0x604 };
38 static int index[CMI8328_MAX] = {[0 ... (CMI8328_MAX-1)] = -1};
39 static char *id[CMI8328_MAX] = {[0 ... (CMI8328_MAX-1)] = NULL};
40 static long port[CMI8328_MAX] = {[0 ... (CMI8328_MAX-1)] = SNDRV_AUTO_PORT};
41 static int irq[CMI8328_MAX] = {[0 ... (CMI8328_MAX-1)] = SNDRV_AUTO_IRQ};
42 static int dma1[CMI8328_MAX] = {[0 ... (CMI8328_MAX-1)] = SNDRV_AUTO_DMA};
43 static int dma2[CMI8328_MAX] = {[0 ... (CMI8328_MAX-1)] = SNDRV_AUTO_DMA};
44 static long mpuport[CMI8328_MAX] = {[0 ... (CMI8328_MAX-1)] = SNDRV_AUTO_PORT};
45 static int mpuirq[CMI8328_MAX] = {[0 ... (CMI8328_MAX-1)] = SNDRV_AUTO_IRQ};
47 static bool gameport[CMI8328_MAX] = {[0 ... (CMI8328_MAX-1)] = true};
[all …]
/linux/drivers/net/wireless/intersil/p54/
H A Dp54usb.h19 #define NET2280_BASE 0x10000000
20 #define NET2280_BASE2 0x20000000
30 #define NET2280_CLK_STOP (0 << LOCAL_CLOCK_FREQUENCY)
44 #define NET2280_DEVINIT 0x00
45 #define NET2280_USBIRQENB1 0x24
46 #define NET2280_IRQSTAT1 0x2c
47 #define NET2280_FIFOCTL 0x38
48 #define NET2280_GPIOCTL 0x50
49 #define NET2280_RELNUM 0x88
50 #define NET2280_EPA_RSP 0x324
[all …]
/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dpci_nrtr_regs.h22 #define mmPCI_NRTR_HBW_MAX_CRED 0x100
24 #define mmPCI_NRTR_LBW_MAX_CRED 0x120
26 #define mmPCI_NRTR_DBG_E_ARB 0x300
28 #define mmPCI_NRTR_DBG_W_ARB 0x304
30 #define mmPCI_NRTR_DBG_N_ARB 0x308
32 #define mmPCI_NRTR_DBG_S_ARB 0x30C
34 #define mmPCI_NRTR_DBG_L_ARB 0x310
36 #define mmPCI_NRTR_DBG_E_ARB_MAX 0x320
38 #define mmPCI_NRTR_DBG_W_ARB_MAX 0x324
40 #define mmPCI_NRTR_DBG_N_ARB_MAX 0x328
[all …]
/linux/drivers/net/ethernet/mediatek/
H A Dmtk_ppe_regs.h7 #define MTK_PPE_GLO_CFG 0x200
8 #define MTK_PPE_GLO_CFG_EN BIT(0)
23 #define MTK_PPE_FLOW_CFG 0x204
42 #define MTK_PPE_IP_PROTO_CHK 0x208
43 #define MTK_PPE_IP_PROTO_CHK_IPV4 GENMASK(15, 0)
46 #define MTK_PPE_TB_CFG 0x21c
47 #define MTK_PPE_TB_CFG_ENTRY_NUM GENMASK(2, 0)
63 #define MTK_PPE_BIND_LMT1 0x230
66 #define MTK_PPE_KEEPALIVE 0x234
86 #define MTK_PPE_TB_BASE 0x220
[all …]
/linux/drivers/net/can/rockchip/
H A Drockchip_canfd.h23 #define RKCANFD_REG_MODE 0x000
39 #define RKCANFD_REG_MODE_WORK_MODE BIT(0)
41 #define RKCANFD_REG_CMD 0x004
43 #define RKCANFD_REG_CMD_TX0_REQ BIT(0)
46 #define RKCANFD_REG_STATE 0x008
53 #define RKCANFD_REG_STATE_RX_BUFFER_FULL BIT(0)
55 #define RKCANFD_REG_INT 0x00c
70 #define RKCANFD_REG_INT_RX_FINISH_INT BIT(0)
95 #define RKCANFD_REG_INT_MASK 0x010
97 #define RKCANFD_REG_DMA_CTL 0x014
[all …]
/linux/arch/x86/include/asm/
H A Dsvm.h16 INTERCEPT_CR = 0,
26 /* Byte offset 000h (word 0) */
27 INTERCEPT_CR0_READ = 0,
157 u64 avic_backing_page; /* Offset 0xe0 */
158 u8 reserved_6[8]; /* Offset 0xe8 */
159 u64 avic_logical_id; /* Offset 0xf0 */
160 u64 avic_physical_id; /* Offset 0xf8 */
164 u16 bus_lock_counter; /* Offset 0x120 */
166 u64 allowed_sev_features; /* Offset 0x138 */
167 u64 guest_sev_features; /* Offset 0x140 */
[all …]
/linux/Documentation/sound/
H A Dalsa-configuration.rst57 (0 = disable debug prints, 1 = normal debug messages,
71 Default: 0
80 the card #0. Similarly, when ``adsp_map=0``, /dev/adsp will be mapped
81 to PCM #0 of the card #0.
83 commas, such like ``dsp_map=0,1``.
98 Default: 0
119 Values: 0 through 31 or negative;
142 appearing card. They can do it by specifying "index=1,0" module
158 the port must be specified. For actual AdLib FM cards it will be 0x388.
170 64:0 OPL2 FM synth OPL2 FM Port
[all …]

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