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Searched +full:0 +full:x31000 (Results 1 – 19 of 19) sorted by relevance

/linux/Documentation/devicetree/bindings/reset/
H A Dqcom,aoss-reset.yaml50 reg = <0xc2a0000 0x31000>;
/linux/arch/arm/boot/dts/unisoc/
H A Drda8810pl.dtsi19 #size-cells = <0>;
21 cpu@0 {
24 reg = <0x0>;
30 reg = <0x100000 0x10000>;
40 ranges = <0x0 0x10000000 0xfffffff>;
44 reg = <0x1a08000 0x1000>;
55 ranges = <0x0 0x20800000 0x100000>;
57 intc: interrupt-controller@0 {
59 reg = <0x0 0x1000>;
69 ranges = <0x0 0x20900000 0x100000>;
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm-hr2.dtsi45 #size-cells = <0>;
47 cpu0: cpu@0 {
51 reg = <0x0>;
64 ranges = <0x00000000 0x19000000 0x00023000>;
68 a9pll: arm_clk@0 {
69 #clock-cells = <0>;
72 reg = <0x0 0x1000>;
77 reg = <0x20200 0x100>;
84 reg = <0x20600 0x20>;
92 reg = <0x20620 0x20>;
[all …]
H A Dbcm-nsp.dtsi54 #size-cells = <0>;
56 cpu0: cpu@0 {
60 reg = <0x0>;
68 secondary-boot-reg = <0xffff0fec>;
69 reg = <0x1>;
82 ranges = <0x00000000 0x19000000 0x00023000>;
86 a9pll: arm_clk@0 {
87 #clock-cells = <0>;
90 reg = <0x00000 0x1000>;
95 reg = <0x20200 0x100>;
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap2430.dtsi18 ranges = <0 0x49000000 0x31000>;
22 reg = <0x6000 0x1000>;
26 #size-cells = <0>;
35 reg = <0x2000 0x1000>;
39 ranges = <0 0x2000 0x1000>;
44 reg = <0x30 0x0154>;
46 #size-cells = <0>;
49 pinctrl-single,function-mask = <0x3f>;
55 reg = <0x270 0x240>;
58 ranges = <0 0x270 0x240>;
[all …]
/linux/drivers/rapidio/switches/
H A Didt_gen3.c18 #define RIO_EM_PW_STAT 0x40020
19 #define RIO_PW_CTL 0x40204
20 #define RIO_PW_CTL_PW_TMR 0xffffff00
21 #define RIO_PW_ROUTE 0x40208
23 #define RIO_EM_DEV_INT_EN 0x40030
25 #define RIO_PLM_SPx_IMP_SPEC_CTL(x) (0x10100 + (x)*0x100)
26 #define RIO_PLM_SPx_IMP_SPEC_CTL_SOFT_RST 0x02000000
28 #define RIO_PLM_SPx_PW_EN(x) (0x10118 + (x)*0x100)
29 #define RIO_PLM_SPx_PW_EN_OK2U 0x40000000
30 #define RIO_PLM_SPx_PW_EN_LINIT 0x10000000
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dt1023si-post.dtsi39 alloc-ranges = <0 0 0x10000 0>;
44 alloc-ranges = <0 0 0x10000 0>;
49 alloc-ranges = <0 0 0x10000 0>;
56 interrupts = <25 2 0 0>;
64 bus-range = <0x0 0xff>;
65 interrupts = <20 2 0 0>;
67 pcie@0 {
68 reg = <0 0 0 0 0>;
73 interrupts = <20 2 0 0>;
74 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
H A Db4si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x200000 */
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
66 pcie@0 {
71 reg = <0 0 0 0 0>;
72 interrupts = <20 2 0 0>;
[all …]
H A Dt2081si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
66 pcie@0 {
67 reg = <0 0 0 0 0>;
[all …]
H A Dt1040si-post.dtsi39 alloc-ranges = <0 0 0x10000 0>;
44 alloc-ranges = <0 0 0x10000 0>;
49 alloc-ranges = <0 0 0x10000 0>;
56 interrupts = <25 2 0 0>;
64 bus-range = <0x0 0xff>;
65 interrupts = <20 2 0 0>;
67 pcie@0 {
68 reg = <0 0 0 0 0>;
73 interrupts = <20 2 0 0>;
74 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
H A Dt4240si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
65 pcie@0 {
70 reg = <0 0 0 0 0>;
[all …]
/linux/drivers/interconnect/qcom/
H A Dsm8650.c29 .port_offsets = { 0xc000 },
31 .urg_fwd = 0,
32 .prio_fwd_disable = 0,
47 .port_offsets = { 0xd000 },
49 .urg_fwd = 0,
50 .prio_fwd_disable = 0,
74 .port_offsets = { 0xe000 },
76 .urg_fwd = 0,
77 .prio_fwd_disable = 0,
92 .port_offsets = { 0xf000 },
[all …]
H A Dmilos.c142 .port_offsets = { 0xc000 },
144 .urg_fwd = 0,
159 .port_offsets = { 0xf200 },
161 .urg_fwd = 0,
176 .port_offsets = { 0x10000 },
178 .urg_fwd = 0,
193 .port_offsets = { 0x14000 },
195 .urg_fwd = 0,
210 .port_offsets = { 0x12000 },
212 .urg_fwd = 0,
[all …]
/linux/drivers/clk/qcom/
H A Dgcc-msm8916.c45 .l_reg = 0x21004,
46 .m_reg = 0x21008,
47 .n_reg = 0x2100c,
48 .config_reg = 0x21010,
49 .mode_reg = 0x21000,
50 .status_reg = 0x2101c,
63 .enable_reg = 0x45000,
64 .enable_mask = BIT(0),
76 .l_reg = 0x20004,
77 .m_reg = 0x20008,
[all …]
H A Dgcc-msm8996.c49 .offset = 0x00000,
52 .enable_reg = 0x52000,
53 .enable_mask = BIT(0),
79 .offset = 0x00000,
94 .enable_reg = 0x5200c,
95 .enable_mask = BIT(0),
111 .enable_reg = 0x5200c,
126 .offset = 0x77000,
129 .enable_reg = 0x52000,
143 .offset = 0x77000,
[all …]
H A Dgcc-ipq5332.c53 .offset = 0x20000,
56 .enable_reg = 0xb000,
57 .enable_mask = BIT(0),
80 .offset = 0x20000,
93 .offset = 0x21000,
96 .enable_reg = 0xb000,
108 .offset = 0x21000,
121 .offset = 0x22000,
124 .enable_reg = 0xb000,
136 .offset = 0x22000,
[all …]
H A Dgcc-msm8939.c53 .l_reg = 0x21004,
54 .m_reg = 0x21008,
55 .n_reg = 0x2100c,
56 .config_reg = 0x21010,
57 .mode_reg = 0x21000,
58 .status_reg = 0x2101c,
71 .enable_reg = 0x45000,
72 .enable_mask = BIT(0),
84 .l_reg = 0x20004,
85 .m_reg = 0x20008,
[all …]
/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb4/
H A Dt4_hw.c54 * at the time it indicated completion is stored there. Returns 0 if the
66 return 0; in t4_wait_op_done_val()
68 if (--attempts == 0) in t4_wait_op_done_val()
167 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a in t4_hw_pci_read_cfg4()
169 * ENABLE is 0 so a simple register write is easier than a in t4_hw_pci_read_cfg4()
172 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0); in t4_hw_pci_read_cfg4()
247 log->cursor = 0; in t4_record_mbox()
249 for (i = 0; i < size / 8; i++) in t4_record_mbox()
252 entry->cmd[i++] = 0; in t4_record_mbox()
277 * The return value is 0 on success or a negative errno on failure. A
[all …]