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/freebsd/sys/dev/bhnd/bcma/
H A Dbcma_dmp.h47 (((_value) & _flag) != 0)
54 #define BCMA_OOB_BUSCONFIG 0x020
55 #define BCMA_OOB_STATUSA 0x100
56 #define BCMA_OOB_STATUSB 0x104
57 #define BCMA_OOB_STATUSC 0x108
58 #define BCMA_OOB_STATUSD 0x10c
59 #define BCMA_OOB_ENABLEA0 0x200
60 #define BCMA_OOB_ENABLEA1 0x204
61 #define BCMA_OOB_ENABLEA2 0x208
62 #define BCMA_OOB_ENABLEA3 0x20c
[all …]
/freebsd/sys/contrib/device-tree/include/dt-bindings/reset/
H A Dhisi,hi6220-resets.h9 #define PERIPH_RSTDIS0_MMC0 0x000
10 #define PERIPH_RSTDIS0_MMC1 0x001
11 #define PERIPH_RSTDIS0_MMC2 0x002
12 #define PERIPH_RSTDIS0_NANDC 0x003
13 #define PERIPH_RSTDIS0_USBOTG_BUS 0x004
14 #define PERIPH_RSTDIS0_POR_PICOPHY 0x005
15 #define PERIPH_RSTDIS0_USBOTG 0x006
16 #define PERIPH_RSTDIS0_USBOTG_32K 0x007
17 #define PERIPH_RSTDIS1_HIFI 0x100
18 #define PERIPH_RSTDIS1_DIGACODEC 0x105
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
H A Dimxrt1170-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
[all …]
H A Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
H A Dimx35-pinfunc.h13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0
14 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0
15 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0
16 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0
17 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0
18 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0
19 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0
20 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0
21 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0
22 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0
[all …]
H A Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
H A Dimx6dl-pinfunc.h13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
H A Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/hisilicon/controller/
H A Dsysctrl.yaml58 cpu 2, reg + 0x4;
59 cpu 3, reg + 0x8;
116 ranges = <0 0x802000 0x1000>;
117 reg = <0x802000 0x1000>;
119 smp-offset = <0x31c>;
120 resume-offset = <0x308>;
[all...]
/freebsd/lib/libpmc/pmu-events/arch/arm64/fujitsu/a64fx/
H A Dcache.json46 "EventCode": "0x49",
52 "EventCode": "0x59",
58 "EventCode": "0x200",
64 "EventCode": "0x202",
70 "EventCode": "0x208",
76 "EventCode": "0x209",
82 "EventCode": "0x300",
88 "EventCode": "0x302",
94 "EventCode": "0x308",
100 "EventCode": "0x309",
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
/freebsd/sys/dev/rtwn/rtl8192c/pci/
H A Dr92ce_reg.h31 #define R92C_PCIE_MIO_INTF 0x0e4
32 #define R92C_PCIE_MIO_INTD 0x0e8
34 #define R92C_PCIE_CTRL_REG 0x300
35 #define R92C_INT_MIG 0x304
36 #define R92C_BCNQ_DESA 0x308
37 #define R92C_HQ_DESA 0x310
38 #define R92C_MGQ_DESA 0x318
39 #define R92C_VOQ_DESA 0x320
40 #define R92C_VIQ_DESA 0x328
41 #define R92C_BEQ_DESA 0x330
[all …]
/freebsd/sys/arm64/coresight/
H A Dcoresight_tmc.h34 #define TMC_RSZ 0x004 /* RAM Size Register */
35 #define TMC_STS 0x00C /* Status Register */
41 #define STS_FULL (1 << 0)
42 #define TMC_RRD 0x010 /* RAM Read Data Register */
43 #define TMC_RRP 0x014 /* RAM Read Pointer Register */
44 #define TMC_RWP 0x018 /* RAM Write Pointer Register */
45 #define TMC_TRG 0x01C /* Trigger Counter Register */
46 #define TMC_CTL 0x020 /* Control Register */
47 #define CTL_TRACECAPTEN (1 << 0) /* Controls trace capture. */
48 #define TMC_RWD 0x024 /* RAM Write Data Register */
[all …]
/freebsd/sys/contrib/dev/rtw88/
H A Dpci.h17 #define RTK_PCI_CTRL 0x300
20 #define REG_DBI_WDATA_V1 0x03E8
21 #define REG_DBI_RDATA_V1 0x03EC
22 #define REG_DBI_FLAG_V1 0x03F0
28 #define REG_MDIO_V1 0x03F4
29 #define REG_PCIE_MIX_CFG 0x03F8
30 #define BITS_MDIO_ADDR_MASK GENMASK(4, 0)
33 #define RTW_PCI_MDIO_PG_OFFS_G1 0
37 #define RTK_PCIE_LINK_CFG 0x0719
40 #define BIT_CLKREQ_N_PAD BIT(0)
[all...]
/freebsd/usr.sbin/bhyve/amd64/
H A Dpci_gvt-d-opregion.h41 /// OpRegion Mailbox 0 Header structure. The OpRegion Header is used to
43 /// Offset 0x0, Size 0x100
46 int8_t sign[0x10]; ///< Offset 0x00 OpRegion Signature
47 uint32_t size; ///< Offset 0x10 OpRegion Size
48 uint32_t over; ///< Offset 0x14 OpRegion Structure Version
49 uint8_t sver[0x20]; ///< Offset 0x18 System BIOS Build Version
50 uint8_t vver[0x10]; ///< Offset 0x38 Video BIOS Build Version
51 uint8_t gver[0x10]; ///< Offset 0x48 Graphic Driver Build Version
52 uint32_t mbox; ///< Offset 0x58 Supported Mailboxes
53 uint32_t dmod; ///< Offset 0x5C Driver Model
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/bcm/
H A Dbrcm,brcmstb.txt49 ranges = <0 0x00 0xf0000000 0x1000000>;
53 reg = <0x404000 0x51c>;
58 reg = <0x3e2400 0x5b4>;
64 reg = <0x452000 0x100>;
94 syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>;
117 syscon = <&sun_top_ctrl 0x304 0x308>;
141 reg = <0x410000 0x400>;
170 "brcm,brcmstb-ddr-phy-v72.0"
182 - compatible : should contain "brcm,brcmstb-ddr-shimphy-v1.0"
199 memc@0 {
[all …]
/freebsd/crypto/heimdal/lib/wind/
H A Dnormalize_table.c9 {0xa0, 1, 0}, /* NO-BREAK SPACE */
10 {0xa8, 2, 1}, /* DIAERESIS */
11 {0xaa, 1, 3}, /* FEMININE ORDINAL INDICATOR */
12 {0xaf, 2, 4}, /* MACRON */
13 {0xb2, 1, 6}, /* SUPERSCRIPT TWO */
14 {0xb3, 1, 7}, /* SUPERSCRIPT THREE */
15 {0xb4, 2, 8}, /* ACUTE ACCENT */
16 {0xb5, 1, 10}, /* MICRO SIGN */
17 {0xb8, 2, 11}, /* CEDILLA */
18 {0xb9, 1, 13}, /* SUPERSCRIPT ONE */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm7445.dtsi17 #size-cells = <0>;
19 cpu@0 {
23 reg = <0>;
50 reg = <0x00 0xffd01000 0x00 0x1000>,
51 <0x00 0xffd02000 0x00 0x2000>,
52 <0x00 0xffd04000 0x00 0x2000>,
53 <0x00 0xffd06000 0x00 0x2000>;
70 ranges = <0 0x00 0xf0000000 0x1000000>;
74 reg = <0x40ab00 0x20>;
84 reg = <0x404000 0x51c>;
[all …]
/freebsd/sys/dev/sk/
H A Dxmaciireg.h43 #define XM_DEVICEID 0x00E0AE20
44 #define XM_XAQTI_OUI 0x00E0AE
46 #define XM_XMAC_REV(x) (((x) & 0x000000E0) >> 5)
48 #define XM_XMAC_REV_B2 0x0
49 #define XM_XMAC_REV_C1 0x1
51 #define XM_MMUCMD 0x0000
52 #define XM_POFF 0x0008
53 #define XM_BURST 0x000C
54 #define XM_VLAN_TAGLEV1 0x0010
55 #define XM_VLAN_TAGLEV2 0x0014
[all …]
/freebsd/sys/dev/ffec/
H A Dif_ffecreg.h41 #define FEC_IER_REG 0x0004
42 #define FEC_IEM_REG 0x0008
61 #define FEC_RDAR_REG 0x0010
64 #define FEC_TDAR_REG 0x0014
67 #define FEC_ECR_REG 0x0024
76 #define FEC_ECR_RESET (1 << 0)
78 #define FEC_MMFR_REG 0x0040
80 #define FEC_MMFR_ST_VALUE (0x01 << FEC_MMFR_ST_SHIFT)
82 #define FEC_MMFR_OP_WRITE (0x01 << FEC_MMFR_OP_SHIFT)
83 #define FEC_MMFR_OP_READ (0x02 << FEC_MMFR_OP_SHIFT)
[all …]
/freebsd/sys/contrib/device-tree/src/mips/brcm/
H A Dbcm7358.dtsi9 #size-cells = <0>;
13 cpu@0 {
16 reg = <0>;
25 #address-cells = <0>;
35 #clock-cells = <0>;
41 #clock-cells = <0>;
51 ranges = <0 0x10000000 0x01000000>;
55 reg = <0x411400 0x30>;
66 reg = <0x403000 0x30>;
75 reg = <0x400000 0xdc>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/hisilicon/
H A Dhisilicon.txt68 cpu 2, reg + 0x4;
69 cpu 3, reg + 0x8;
79 reg = <0xfc802000 0x1000>;
80 smp-offset = <0x31c>;
81 resume-offset = <0x308>;
82 reboot-offset = <0x4>;
103 reg = <0x8a20000 0x1000>;
125 reg = <0x0 0xf7030000 0x0 0x2000>;
145 reg = <0x0 0xf7800000 0x0 0x2000>;
165 reg = <0x0 0xf4410000 0x0 0x1000>;
[all …]
/freebsd/sys/powerpc/pseries/
H A Dphyp-hvcall.h37 #define H_SUCCESS 0
172 #define H_SET_MODE_RSRC_CIABR 0x1 /* All versions */
173 #define H_SET_MODE_RSRC_DAWR0 0x2 /* All versions */
174 #define H_SET_MODE_RSRC_INTR_TRANS_MODE 0x3 /* All versions */
175 #define H_SET_MODE_RSRC_ILE 0x4 /* PAPR 2.8 / ISA 2.07 */
176 #define H_SET_MODE_RSRC_DAWR1 0x5 /* ISA 3.1 Future support */
179 #define PROC_TABLE_OP_MASK 0x18
180 #define PROC_TABLE_DEREG 0x10
181 #define PROC_TABLE_NEW 0x18
182 #define PROC_TABLE_TYPE_MASK 0x06
[all …]

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