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/titanic_52/usr/src/cmd/luxadm/
H A Dfcalupdate.c73 #define FEPROM_READ_MEMORY 0x00
74 #define FEPROM_ERASE 0x20
75 #define FEPROM_ERASE_VERIFY 0xa0
76 #define FEPROM_PROGRAM 0x40
77 #define FEPROM_PROGRAM_VERIFY 0xc0
78 #define FEPROM_RESET 0xff
81 #define FOUND 0
83 #define PROM_SIZ 0x20010
92 #define PROM_SIZ_ROUNDED 0x22000
93 #define SAMPLE_SIZ 0x10
[all...]
H A Derrorcodes.h56 #define L_SCSI_ERROR 0x10000
59 #define L_RD_INVLD_TRNSFR_LEN 0x11002
62 #define L_RD_NO_DISK_ELEM 0x11003
65 #define L_ILLEGAL_MODE_SENSE_PAGE 0x11004
68 #define L_INVALID_NO_OF_ENVSEN_PAGES 0x11005
71 #define L_INVALID_BUF_LEN 0x11006
74 #define L_SCSI_VHCI_ERROR 0x11007
75 #define L_SCSI_VHCI_ALREADY_ACTIVE 0x11008
76 #define L_SCSI_VHCI_NO_STANDBY 0x11009
77 #define L_SCSI_VHCI_FAILOVER_NOTSUP 0x1100
[all...]
/titanic_52/usr/src/uts/sun/sys/
H A Dsocalreg.h67 #define SOCAL_CR_SBUS_BURST_SIZE_MASK 0x007
68 #define SOCAL_CR_SBUS_BURST_SIZE_64BIT_MASK 0x700
72 #define SOCAL_CR_BURST_4 0x0
73 #define SOCAL_CR_BURST_8 0x3
74 #define SOCAL_CR_BURST_16 0x4
75 #define SOCAL_CR_BURST_32 0x5
76 #define SOCAL_CR_BURST_64 0x6
77 #define SOCAL_CR_BURST_128 0x7
79 #define SOCAL_CR_SBUS_ENHANCED 0x08
80 #define SOCAL_CR_SBUS_PARITY_CHK 0x1
[all...]
/titanic_52/usr/src/uts/common/sys/scsi/conf/
H A Dautoconf.h40 #define SCSI_DEBUG_TGT 0x1 /* debug statements in target drivers */
41 #define SCSI_DEBUG_LIB 0x2 /* debug statements in library */
42 #define SCSI_DEBUG_HA 0x4 /* debug statements in host adapters */
47 #define SCSI_OPTIONS_LINK 0x10 /* Global linked commands */
48 #define SCSI_OPTIONS_TAG 0x80 /* Global tagged command support */
53 #define SCSI_OPTIONS_DR 0x8 /* Global disconnect/reconnect */
54 #define SCSI_OPTIONS_SYNC 0x20 /* Global synchronous xfer capability */
55 #define SCSI_OPTIONS_PARITY 0x40 /* Global parity support */
56 #define SCSI_OPTIONS_FAST 0x100 /* Global FAST scsi support */
57 #define SCSI_OPTIONS_WIDE 0x20
[all...]
/titanic_52/usr/src/boot/sys/boot/fdt/dts/arm/
H A Ddockstar.dts53 #size-cells = <0>;
55 cpu@0 {
58 reg = <0x0>;
61 d-cache-size = <0x4000>; // L1, 16K
62 i-cache-size = <0x4000>; // L1, 16K
63 timebase-frequency = <0>;
64 bus-frequency = <0>;
65 clock-frequency = <0>;
71 reg = <0x0 0x800000
[all...]
H A Dsheevaplug.dts53 #size-cells = <0>;
55 cpu@0 {
58 reg = <0x0>;
61 d-cache-size = <0x4000>; // L1, 16K
62 i-cache-size = <0x4000>; // L1, 16K
63 timebase-frequency = <0>;
64 bus-frequency = <0>;
65 clock-frequency = <0>;
71 reg = <0x0 0x2000000
[all...]
H A Ddb88f6281.dts54 #size-cells = <0>;
56 cpu@0 {
59 reg = <0x0>;
62 d-cache-size = <0x4000>; // L1, 16K
63 i-cache-size = <0x4000>; // L1, 16K
64 timebase-frequency = <0>;
65 bus-frequency = <0>;
66 clock-frequency = <0>;
72 reg = <0x0 0x2000000
[all...]
H A Ddreamplug-1001N.dts58 #size-cells = <0>;
60 cpu@0 {
63 reg = <0x0>;
66 d-cache-size = <0x4000>; // L1, 16K
67 i-cache-size = <0x4000>; // L1, 16K
68 timebase-frequency = <0>;
69 bus-frequency = <0>;
70 clock-frequency = <0>;
77 reg = <0x0 0x2000000
[all...]
H A Ddreamplug-1001.dts58 #size-cells = <0>;
60 cpu@0 {
63 reg = <0x0>;
66 d-cache-size = <0x4000>; // L1, 16K
67 i-cache-size = <0x4000>; // L1, 16K
68 timebase-frequency = <0>;
69 bus-frequency = <0>;
70 clock-frequency = <0>;
77 reg = <0x0 0x2000000
[all...]
H A Darmada-38x.dtsi79 pcie-mem-aperture = <0xe0000000 0x8000000>;
80 pcie-io-aperture = <0xe8000000 0x100000>;
84 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
89 reg = <MBUS_ID(0xf0, 0x0
[all...]
/titanic_52/usr/src/lib/hal/libhal-storage/common/
H A Dlibhal-storage.h35 #if 0
49 LIBHAL_STORAGE_ICON_DRIVE_REMOVABLE_DISK = 0x10000,
50 LIBHAL_STORAGE_ICON_DRIVE_REMOVABLE_DISK_IDE = 0x10001,
51 LIBHAL_STORAGE_ICON_DRIVE_REMOVABLE_DISK_SCSI = 0x10002,
52 LIBHAL_STORAGE_ICON_DRIVE_REMOVABLE_DISK_USB = 0x10003,
53 LIBHAL_STORAGE_ICON_DRIVE_REMOVABLE_DISK_IEEE1394 = 0x10004,
54 LIBHAL_STORAGE_ICON_DRIVE_DISK = 0x10100,
55 LIBHAL_STORAGE_ICON_DRIVE_DISK_IDE = 0x10101,
56 LIBHAL_STORAGE_ICON_DRIVE_DISK_SCSI = 0x10102,
57 LIBHAL_STORAGE_ICON_DRIVE_DISK_USB = 0x1010
[all...]
/titanic_52/usr/src/lib/storage/common/
H A Dstgcom.h56 #define DRV_PART_NAME ",0:c,raw"
93 #define L_SCSI_ERROR 0x10000
96 #define L_RD_INVLD_TRNSFR_LEN 0x11002
99 #define L_RD_NO_DISK_ELEM 0x11003
102 #define L_ILLEGAL_MODE_SENSE_PAGE 0x11004
105 #define L_INVALID_NO_OF_ENVSEN_PAGES 0x11005
108 #define L_INVALID_BUF_LEN 0x11006
111 #define L_SCSI_VHCI_ERROR 0x11007
112 #define L_SCSI_VHCI_ALREADY_ACTIVE 0x11008
113 #define L_SCSI_VHCI_NO_STANDBY 0x1100
[all...]
/titanic_52/usr/src/uts/common/sys/scsi/adapters/pmcs/
H A Dpmcs_reg.h36 #define PMCS_VENDOR_ID 0x11F8
37 #define PMCS_DEVICE_ID 0x8001
39 #define PMCS_PM8001_REV_A 0
77 #define PMCS_MSGU_IBDB 0x04 /* Inbound Doorbell */
78 #define PMCS_MSGU_IBDB_CLEAR 0x20 /* InBound Doorbell Clear */
79 #define PMCS_MSGU_OBDB 0x3c /* OutBound Doorbell */
80 #define PMCS_MSGU_OBDB_CLEAR 0x40 /* OutBound Doorbell Clear */
81 #define PMCS_MSGU_SCRATCH0 0x44 /* Scratchpad 0 */
82 #define PMCS_MSGU_SCRATCH1 0x4
[all...]
/titanic_52/usr/src/cmd/cpio/
H A Dcpio.h43 #define OCa 0x1
44 #define OCb 0x2
45 #define OCc 0x4
46 #define OCd 0x8
47 #define OCf 0x10
48 #define OCi 0x20
49 #define OCk 0x40
50 #define OCl 0x80
51 #define OCm 0x100
52 #define OCo 0x20
[all...]
/titanic_52/usr/src/uts/common/sys/nxge/
H A Dnxge_defs.h37 #define PIO 0x000000
38 #define FZC_PIO 0x080000
39 #define RESERVED_1 0x100000
40 #define FZC_MAC 0x180000
41 #define RESERVED_2 0x200000
42 #define FZC_IPP 0x280000
43 #define FFLP 0x300000
44 #define FZC_FFLP 0x380000
45 #define PIO_VADDR 0x400000
46 #define RESERVED_3 0x48000
[all...]
/titanic_52/usr/src/boot/sys/boot/fdt/dts/powerpc/
H A Dmpc8555cds.dts82 #size-cells = <0>;
84 PowerPC,8555@0 {
86 reg = <0x0>;
89 d-cache-size = <0x8000>; // L1, 32K
90 i-cache-size = <0x8000>; // L1, 32K
91 timebase-frequency = <0>; // 33 MHz, from uboot
92 bus-frequency = <0>; // 166 MHz
93 clock-frequency = <0>; // 825 MHz, from uboot
100 reg = <0x0 0x1000000
[all...]
H A Dp1020rdb.dts56 #size-cells = <0>;
58 PowerPC,P1020@0 {
60 reg = <0x0>;
66 reg = <0x1>;
79 reg = <0 0xffe05000 0 0x1000>;
84 ranges = <0x0 0x
[all...]
H A Dp2020ds.dts82 #size-cells = <0>;
84 PowerPC,P2020@0 {
86 reg = <0x0>;
92 reg = <0x1>;
105 reg = <0 0xffe05000 0 0x1000>;
109 ranges = <0x0 0x
[all...]
H A Dmpc8572ds.dts84 #size-cells = <0>;
86 PowerPC,8572@0 {
88 reg = <0x0>;
91 d-cache-size = <0x8000>; // L1, 32K
92 i-cache-size = <0x8000>; // L1, 32K
93 timebase-frequency = <0>;
94 bus-frequency = <0>;
95 clock-frequency = <0>;
101 reg = <0x1>;
104 d-cache-size = <0x800
[all...]
/titanic_52/usr/src/uts/common/io/hxge/
H A Dhxge_pfc_hw.h35 #define PFC_BASE_ADDR 0X0200000
37 #define PFC_VLAN_TABLE (PFC_BASE_ADDR + 0x0)
38 #define PFC_VLAN_CTRL (PFC_BASE_ADDR + 0x9000)
39 #define PFC_MAC_ADDR (PFC_BASE_ADDR + 0x10000)
40 #define PFC_MAC_ADDR_MASK (PFC_BASE_ADDR + 0x10080)
41 #define PFC_HASH_TABLE (PFC_BASE_ADDR + 0x10100)
42 #define PFC_L2_CLASS_CONFIG (PFC_BASE_ADDR + 0x20000)
43 #define PFC_L3_CLASS_CONFIG (PFC_BASE_ADDR + 0x20030)
44 #define PFC_TCAM_KEY0 (PFC_BASE_ADDR + 0x20090)
45 #define PFC_TCAM_KEY1 (PFC_BASE_ADDR + 0x2009
[all...]
/titanic_52/usr/src/uts/common/io/cxgbe/common/
H A Dcommon.h46 MEMWIN0_BASE = 0x1b800,
48 MEMWIN1_BASE = 0x28000,
50 MEMWIN2_BASE = 0x30000,
58 PAUSE_RX = 1 << 0,
81 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
111 u64 rx_ppp0; /* # of received PPP prio 0 frames */
120 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
124 u64 rx_trunc0; /* buffer-group 0 truncated packets */
270 T4_REV_A = 0,
[all...]
/titanic_52/usr/src/uts/common/io/ntxn/
H A Dunm_inc.h64 #define bzero(A, B) memset((A), 0, (B))
79 #define UNM_HW_H0_CH_HUB_ADR 0x05
80 #define UNM_HW_H1_CH_HUB_ADR 0x0E
81 #define UNM_HW_H2_CH_HUB_ADR 0x03
82 #define UNM_HW_H3_CH_HUB_ADR 0x01
83 #define UNM_HW_H4_CH_HUB_ADR 0x06
84 #define UNM_HW_H5_CH_HUB_ADR 0x07
85 #define UNM_HW_H6_CH_HUB_ADR 0x08
91 /* Hub 0 */
92 #define UNM_HW_MN_CRB_AGT_ADR 0x1
[all...]
/titanic_52/usr/src/uts/common/sys/
H A Dpcie.h41 #define PCIE_PCIECAP 0x02 /* PCI-e Capability Reg */
42 #define PCIE_DEVCAP 0x04 /* Device Capability */
43 #define PCIE_DEVCTL 0x08 /* Device Control */
44 #define PCIE_DEVSTS 0x0A /* Device Status */
45 #define PCIE_LINKCAP 0x0C /* Link Capability */
46 #define PCIE_LINKCTL 0x10 /* Link Control */
47 #define PCIE_LINKSTS 0x12 /* Link Status */
48 #define PCIE_SLOTCAP 0x14 /* Slot Capability */
49 #define PCIE_SLOTCTL 0x18 /* Slot Control */
50 #define PCIE_SLOTSTS 0x1
[all...]
/titanic_52/usr/src/lib/efcode/engine/
H A Dfcode.c37 int fcode_impl_count = 0;
55 if ((token) && (token < 0x10)) { in get_next_token()
104 header(env, name, strlen(name), 0); in do_code()
122 env->interpretting = 0; in end0()
128 env->interpretting = 0; in end1()
151 ASSERT((which < 3) && (which >= 0)); in branch_common()
155 if (direction >= 0) { in branch_common()
159 PUSH(DS, 0); in branch_common()
196 branch_common(env, offset, 0, 1); in bbranch()
204 branch_common(env, offset, 1, 0); in bqbranch()
[all...]
/titanic_52/usr/src/uts/common/io/audio/drv/audiols/
H A Daudiols.c60 0x00000000, /* low DMA address range */
61 0xffffffff, /* high DMA address range */
62 0x000fffff, /* DMA counter (16 bits only in Audigy LS) */
64 0x3c, /* DMA burstsizes */
66 0xffffffff, /* max DMA xfer size */
67 0xffffffff, /* segment boundary */
70 0 /* Bus specific DMA flags */
155 OUTL(dev, PR, (reg << 16) | (chn & 0xffff)); in read_chan()
168 OUTL(dev, PR, (reg << 16) | (chn & 0x7)); in write_chan()
177 return (read_chan(dev, reg, 0)); in read_reg()
[all...]

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