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/linux/arch/arm64/boot/dts/apple/
H A Dt6002.dtsi71 reg = <0x0 0x800>;
73 cpu-release-addr = <0 0>; /* To be filled by loader */
75 i-cache-size = <0x20000>;
76 d-cache-size = <0x10000>;
85 reg = <0x0 0x801>;
87 cpu-release-addr = <0 0>; /* To be filled by loader */
89 i-cache-size = <0x20000>;
90 d-cache-size = <0x10000>;
99 reg = <0x0 0x10900>;
101 cpu-release-addr = <0 0>; /* To be filled by loader */
[all …]
H A Dt600x-common.dtsi20 #size-cells = <0>;
63 cpu_e00: cpu@0 {
66 reg = <0x0 0x0>;
68 cpu-release-addr = <0 0>; /* To be filled by loader */
70 i-cache-size = <0x20000>;
71 d-cache-size = <0x10000>;
80 reg = <0x0 0x1>;
82 cpu-release-addr = <0 0>; /* To be filled by loader */
84 i-cache-size = <0x20000>;
85 d-cache-size = <0x10000>;
[all …]
H A Dt8112-j473.dts41 ethernet0: ethernet@0,0 {
42 reg = <0x30000 0x0 0x0 0x0 0x0>;
/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dcpu_ca53_cfg_masks.h23 #define CPU_CA53_CFG_ARM_CFG_AA64NAA32_SHIFT 0
24 #define CPU_CA53_CFG_ARM_CFG_AA64NAA32_MASK 0x3
26 #define CPU_CA53_CFG_ARM_CFG_END_MASK 0x30
28 #define CPU_CA53_CFG_ARM_CFG_TE_MASK 0x300
30 #define CPU_CA53_CFG_ARM_CFG_VINITHI_MASK 0x3000
33 #define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_SHIFT 0
34 #define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_MASK 0xFFFFFFFF
37 #define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_SHIFT 0
38 #define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_MASK 0xFF
41 #define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT 0
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dpq3-sec4.4-0.dtsi2 * PQ3 Sec/Crypto 4.4 device tree stub [ controller @ offset 0x30000 ]
36 compatible = "fsl,sec-v4.4", "fsl,sec-v4.0";
40 ranges = <0x0 0x30000 0x10000>;
41 reg = <0x30000 0x10000>;
42 interrupts = <58 2 0 0>;
45 compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
46 reg = <0x1000 0x1000>;
47 interrupts = <45 2 0 0>;
51 compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
52 reg = <0x2000 0x1000>;
[all …]
H A Dpq3-sec2.1-0.dtsi2 * PQ3 Sec/Crypto 2.1 device tree stub [ controller @ offset 0x30000 ]
36 compatible = "fsl,sec2.1", "fsl,sec2.0";
37 reg = <0x30000 0x10000>;
38 interrupts = <45 2 0 0>;
41 fsl,exec-units-mask = <0xfe>;
42 fsl,descriptor-types-mask = <0x12b0ebf>;
H A Dpq3-sec3.0-0.dtsi2 * PQ3 Sec/Crypto 3.0 device tree stub [ controller @ offset 0x30000 ]
36 compatible = "fsl,sec3.0",
38 "fsl,sec2.0";
39 reg = <0x30000 0x10000>;
40 interrupts = <45 2 0 0 58 2 0 0>;
43 fsl,exec-units-mask = <0x9fe>;
44 fsl,descriptor-types-mask = <0x3ab0ebf>;
H A Dpq3-sec3.1-0.dtsi2 * PQ3 Sec/Crypto 3.1 device tree stub [ controller @ offset 0x30000 ]
36 compatible = "fsl,sec3.1", "fsl,sec3.0",
38 "fsl,sec2.0";
39 reg = <0x30000 0x10000>;
40 interrupts = <45 2 0 0 58 2 0 0>;
43 fsl,exec-units-mask = <0xbfe>;
44 fsl,descriptor-types-mask = <0x3ab0ebf>;
H A Dpq3-sec3.3-0.dtsi2 * PQ3 Sec/Crypto 3.3 device tree stub [ controller @ offset 0x30000 ]
36 compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
38 "fsl,sec2.0";
39 reg = <0x30000 0x10000>;
40 interrupts = <45 2 0 0 58 2 0 0>;
43 fsl,exec-units-mask = <0x97c>;
44 fsl,descriptor-types-mask = <0x3a30abf>;
/linux/arch/mips/boot/dts/ralink/
H A Drt3052_eval.dts10 memory@0 {
12 reg = <0x0 0x2000000>;
21 reg = <0x1f000000 0x800000>;
28 partition@0 {
30 reg = <0x0 0x30000>;
35 reg = <0x30000 0x10000>;
40 reg = <0x40000 0x10000>;
45 reg = <0x50000 0x7b0000>;
H A Dmt7621-gnubee-gb-pc1.dts13 memory@0 {
15 reg = <0x00000000 0x1c000000>,
16 <0x20000000 0x04000000>;
57 flash@0 {
61 reg = <0>;
65 partition@0 {
67 reg = <0x0 0x30000>;
73 reg = <0x30000 0x10000>;
79 reg = <0x40000 0x10000>;
85 reg = <0x50000 0x1fb0000>;
[all …]
H A Dmt7621-gnubee-gb-pc2.dts13 memory@0 {
15 reg = <0x00000000 0x1c000000>,
16 <0x20000000 0x04000000>;
77 flash@0 {
81 reg = <0>;
85 partition@0 {
87 reg = <0x0 0x30000>;
93 reg = <0x30000 0x10000>;
99 reg = <0x40000 0x10000>;
105 reg = <0x50000 0x1fb0000>;
[all …]
/linux/tools/testing/selftests/bpf/progs/
H A Dtest_ringbuf_write.c14 int pid = 0;
17 long passed = 0;
18 long discarded = 0;
27 return 0; in test_ringbuf_write()
29 sample1 = bpf_ringbuf_reserve(&ringbuf, 0x30000, 0); in test_ringbuf_write()
31 return 0; in test_ringbuf_write()
33 sample2 = bpf_ringbuf_reserve(&ringbuf, 0x30000, 0); in test_ringbuf_write()
35 bpf_ringbuf_discard(sample1, 0); in test_ringbuf_write()
37 return 0; in test_ringbuf_write()
43 bpf_ringbuf_discard(sample1, 0); in test_ringbuf_write()
[all …]
/linux/arch/s390/include/asm/
H A Dspinlock.h33 "m" (((struct lowcore *)0)->spinlock_lockval)); in spinlock_lockval()
66 return lock.lock == 0; in arch_spin_value_unlocked()
71 return READ_ONCE(lp->lock) != 0; in arch_spin_is_locked()
76 int old = 0; in arch_spin_trylock_once()
100 ALTERNATIVE("nop", ".insn rre,0xb2fa0000,7,0", ALT_FACILITY(49)) /* NIAI 7 */ in arch_spin_unlock()
101 " mvhhi %[lock],0" in arch_spin_unlock()
129 if (old & 0xffff0000) in arch_read_lock()
140 int old = 0; in arch_write_lock()
142 if (!arch_try_cmpxchg(&rw->cnts, &old, 0x30000)) in arch_write_lock()
148 __atomic_add_barrier(-0x30000, &rw->cnts); in arch_write_unlock()
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Dkirkwood-dir665.dts18 reg = <0x00000000 0x8000000>; /* 128 MB */
28 pinctrl-0 =< &pmx_led_usb
81 flash@0 {
86 reg = <0>;
88 partition@0 {
90 reg = <0x0 0x30000>;
96 reg = <0x30000 0x10000>;
102 reg = <0x40000 0x180000>;
107 reg = <0x1c0000 0xe00000>;
112 reg = <0xfc0000 0x10000>;
[all …]
H A Dorion5x-linkstation.dtsi55 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
56 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
57 <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x40000>;
67 #size-cells = <0>;
68 pinctrl-0 = <&pmx_power_usb &pmx_power_hdd>;
109 flash@0 {
111 reg = <0 0x40000>;
119 header@0 {
120 reg = <0 0x30000>;
125 reg = <0x30000 0xF000>;
[all …]
/linux/drivers/clk/imx/
H A Dclk-imx8qxp-lpcg.h11 #define LSIO_PWM_0_LPCG 0x00000
12 #define LSIO_PWM_1_LPCG 0x10000
13 #define LSIO_PWM_2_LPCG 0x20000
14 #define LSIO_PWM_3_LPCG 0x30000
15 #define LSIO_PWM_4_LPCG 0x40000
16 #define LSIO_PWM_5_LPCG 0x50000
17 #define LSIO_PWM_6_LPCG 0x60000
18 #define LSIO_PWM_7_LPCG 0x70000
19 #define LSIO_GPIO_0_LPCG 0x80000
20 #define LSIO_GPIO_1_LPCG 0x90000
[all …]
/linux/arch/arm/mach-dove/
H A Ddove.h14 * e0000000 @runtime 128M PCIe-0 Memory space
18 * f2000000 fee00000 1M PCIe-0 I/O space
22 #define DOVE_CESA_PHYS_BASE 0xc8000000
23 #define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000)
26 #define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000
29 #define DOVE_PCIE1_MEM_PHYS_BASE 0xe8000000
32 #define DOVE_BOOTROM_PHYS_BASE 0xf8000000
35 #define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000
36 #define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000)
39 #define DOVE_SB_REGS_PHYS_BASE 0xf1000000
[all …]
/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Drot0_masks.h24 #define ROT0_KMD_MODE_EN_SHIFT 0
25 #define ROT0_KMD_MODE_EN_MASK 0x1
28 #define ROT0_CPL_QUEUE_EN_Q_EN_SHIFT 0
29 #define ROT0_CPL_QUEUE_EN_Q_EN_MASK 0x1
32 #define ROT0_CPL_QUEUE_ADDR_L_VAL_SHIFT 0
33 #define ROT0_CPL_QUEUE_ADDR_L_VAL_MASK 0xFFFFFFFF
36 #define ROT0_CPL_QUEUE_ADDR_H_VAL_SHIFT 0
37 #define ROT0_CPL_QUEUE_ADDR_H_VAL_MASK 0xFFFFFFFF
40 #define ROT0_CPL_QUEUE_DATA_VAL_SHIFT 0
41 #define ROT0_CPL_QUEUE_DATA_VAL_MASK 0xFFFFFFFF
[all …]
/linux/drivers/gpu/drm/xe/abi/
H A Dgsc_proxy_commands_abi.h18 * Bits 0-7: type of the proxy message (see enum xe_gsc_proxy_type)
23 #define GSC_PROXY_TYPE GENMASK(7, 0)
28 #define GSC_PROXY_ADDRESSING_KMD 0x10000
29 #define GSC_PROXY_ADDRESSING_GSC 0x20000
30 #define GSC_PROXY_ADDRESSING_CSME 0x30000
37 GSC_PROXY_MSG_TYPE_PROXY_INVALID = 0,
/linux/arch/arm64/boot/dts/qcom/
H A Dsc8280xp-el2.dtso23 iommu-map = <0 &pcie_smmu 0x20000 0x10000>;
27 iommu-map = <0 &pcie_smmu 0x30000 0x10000>;
31 iommu-map = <0 &pcie_smmu 0x40000 0x10000>;
35 iommu-map = <0 &pcie_smmu 0x50000 0x10000>;
39 iommu-map = <0 &pcie_smmu 0x60000 0x10000>;
/linux/drivers/soc/tegra/cbb/
H A Dtegra234-cbb.c8 * Error types supported by CBB2.0 are:
27 #define FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0 0x0
28 #define FABRIC_EN_CFG_STATUS_0_0 0x40
29 #define FABRIC_EN_CFG_ADDR_INDEX_0_0 0x60
30 #define FABRIC_EN_CFG_ADDR_LOW_0 0x80
31 #define FABRIC_EN_CFG_ADDR_HI_0 0x84
33 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_INDEX_0_0 0x100
34 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_LOW_0 0x140
35 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_HI_0 0x144
37 #define FABRIC_MN_INITIATOR_ERR_EN_0 0x200
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,qcs404-turingcc.yaml42 reg = <0x00800000 0x30000>;
/linux/drivers/net/wireless/mediatek/mt76/mt7615/
H A Dmmio.c15 [MT_TOP_CFG_BASE] = 0x01000,
16 [MT_HW_BASE] = 0x01000,
17 [MT_PCIE_REMAP_2] = 0x02504,
18 [MT_ARB_BASE] = 0x20c00,
19 [MT_HIF_BASE] = 0x04000,
20 [MT_CSR_BASE] = 0x07000,
21 [MT_PLE_BASE] = 0x08000,
22 [MT_PSE_BASE] = 0x0c000,
23 [MT_CFG_BASE] = 0x20200,
24 [MT_AGG_BASE] = 0x20a00,
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8-ss-security.dtsi12 ranges = <0x31400000 0x0 0x31400000 0x90000>;
15 compatible = "fsl,imx8qm-caam", "fsl,sec-v4.0";
16 reg = <0x31400000 0x90000>;
20 ranges = <0 0x31400000 0x90000>;
25 compatible = "fsl,imx8qm-job-ring", "fsl,sec-v4.0-job-ring";
26 reg = <0x30000 0x10000>;
32 compatible = "fsl,imx8qm-job-ring", "fsl,sec-v4.0-job-ring";
33 reg = <0x40000 0x10000>;

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