Lines Matching +full:0 +full:x30000

16 		#size-cells = <0>;
59 		cpu_e00: cpu@0 {
62 			reg = <0x0 0x0>;
64 			cpu-release-addr = <0 0>; /* To be filled by loader */
66 			i-cache-size = <0x20000>;
67 			d-cache-size = <0x10000>;
76 			reg = <0x0 0x1>;
78 			cpu-release-addr = <0 0>; /* To be filled by loader */
80 			i-cache-size = <0x20000>;
81 			d-cache-size = <0x10000>;
90 			reg = <0x0 0x10100>;
92 			cpu-release-addr = <0 0>; /* To be filled by loader */
94 			i-cache-size = <0x30000>;
95 			d-cache-size = <0x20000>;
104 			reg = <0x0 0x10101>;
106 			cpu-release-addr = <0 0>; /* To be filled by loader */
108 			i-cache-size = <0x30000>;
109 			d-cache-size = <0x20000>;
118 			reg = <0x0 0x10102>;
120 			cpu-release-addr = <0 0>; /* To be filled by loader */
122 			i-cache-size = <0x30000>;
123 			d-cache-size = <0x20000>;
132 			reg = <0x0 0x10103>;
134 			cpu-release-addr = <0 0>; /* To be filled by loader */
136 			i-cache-size = <0x30000>;
137 			d-cache-size = <0x20000>;
146 			reg = <0x0 0x10200>;
148 			cpu-release-addr = <0 0>; /* To be filled by loader */
150 			i-cache-size = <0x30000>;
151 			d-cache-size = <0x20000>;
160 			reg = <0x0 0x10201>;
162 			cpu-release-addr = <0 0>; /* To be filled by loader */
164 			i-cache-size = <0x30000>;
165 			d-cache-size = <0x20000>;
174 			reg = <0x0 0x10202>;
176 			cpu-release-addr = <0 0>; /* To be filled by loader */
178 			i-cache-size = <0x30000>;
179 			d-cache-size = <0x20000>;
188 			reg = <0x0 0x10203>;
190 			cpu-release-addr = <0 0>; /* To be filled by loader */
192 			i-cache-size = <0x30000>;
193 			d-cache-size = <0x20000>;
199 		l2_cache_0: l2-cache-0 {
203 			cache-size = <0x400000>;
210 			cache-size = <0xc00000>;
217 			cache-size = <0xc00000>;
221 	icestorm_opp: opp-table-0 {
339 		interrupts = <AIC_FIQ 0 AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH>;
345 		interrupts = <AIC_FIQ 0 AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH>;
352 		interrupts = <AIC_FIQ 0 AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>,
353 			     <AIC_FIQ 0 AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>,
354 			     <AIC_FIQ 0 AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>,
355 			     <AIC_FIQ 0 AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>;
360 		#clock-cells = <0>;
371 		#clock-cells = <0>;