1*d0c2eccfSRayyan Ansari# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*d0c2eccfSRayyan Ansari%YAML 1.2 3*d0c2eccfSRayyan Ansari--- 4*d0c2eccfSRayyan Ansari$id: http://devicetree.org/schemas/clock/qcom,qcs404-turingcc.yaml# 5*d0c2eccfSRayyan Ansari$schema: http://devicetree.org/meta-schemas/core.yaml# 6*d0c2eccfSRayyan Ansari 7*d0c2eccfSRayyan Ansarititle: Qualcomm Turing Clock & Reset Controller on QCS404 8*d0c2eccfSRayyan Ansari 9*d0c2eccfSRayyan Ansarimaintainers: 10*d0c2eccfSRayyan Ansari - Bjorn Andersson <andersson@kernel.org> 11*d0c2eccfSRayyan Ansari 12*d0c2eccfSRayyan Ansariproperties: 13*d0c2eccfSRayyan Ansari compatible: 14*d0c2eccfSRayyan Ansari const: qcom,qcs404-turingcc 15*d0c2eccfSRayyan Ansari 16*d0c2eccfSRayyan Ansari reg: 17*d0c2eccfSRayyan Ansari maxItems: 1 18*d0c2eccfSRayyan Ansari 19*d0c2eccfSRayyan Ansari clocks: 20*d0c2eccfSRayyan Ansari maxItems: 1 21*d0c2eccfSRayyan Ansari 22*d0c2eccfSRayyan Ansari '#clock-cells': 23*d0c2eccfSRayyan Ansari const: 1 24*d0c2eccfSRayyan Ansari 25*d0c2eccfSRayyan Ansari '#reset-cells': 26*d0c2eccfSRayyan Ansari const: 1 27*d0c2eccfSRayyan Ansari 28*d0c2eccfSRayyan Ansarirequired: 29*d0c2eccfSRayyan Ansari - compatible 30*d0c2eccfSRayyan Ansari - reg 31*d0c2eccfSRayyan Ansari - clocks 32*d0c2eccfSRayyan Ansari - '#clock-cells' 33*d0c2eccfSRayyan Ansari - '#reset-cells' 34*d0c2eccfSRayyan Ansari 35*d0c2eccfSRayyan AnsariadditionalProperties: false 36*d0c2eccfSRayyan Ansari 37*d0c2eccfSRayyan Ansariexamples: 38*d0c2eccfSRayyan Ansari - | 39*d0c2eccfSRayyan Ansari #include <dt-bindings/clock/qcom,gcc-qcs404.h> 40*d0c2eccfSRayyan Ansari clock-controller@800000 { 41*d0c2eccfSRayyan Ansari compatible = "qcom,qcs404-turingcc"; 42*d0c2eccfSRayyan Ansari reg = <0x00800000 0x30000>; 43*d0c2eccfSRayyan Ansari clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>; 44*d0c2eccfSRayyan Ansari 45*d0c2eccfSRayyan Ansari #clock-cells = <1>; 46*d0c2eccfSRayyan Ansari #reset-cells = <1>; 47*d0c2eccfSRayyan Ansari }; 48