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123

/freebsd/sys/dev/clk/allwinner/
H A Dccu_h3.c62 #define CLK_PLL_CPUX 0
97 CCU_RESET(RST_USB_PHY0, 0xcc, 0)
98 CCU_RESET(RST_USB_PHY1, 0xcc, 1)
99 CCU_RESET(RST_USB_PHY2, 0xcc, 2)
100 CCU_RESET(RST_USB_PHY3, 0xcc, 3)
102 CCU_RESET(RST_MBUS, 0xfc, 31)
104 CCU_RESET(RST_BUS_CE, 0x2c0, 5)
105 CCU_RESET(RST_BUS_DMA, 0x2c0, 6)
106 CCU_RESET(RST_BUS_MMC0, 0x2c0, 8)
107 CCU_RESET(RST_BUS_MMC1, 0x2c0, 9)
[all …]
H A Dccu_a64.c52 #define CLK_OSC_12M 0
84 CCU_RESET(RST_USB_PHY0, 0x0cc, 0)
85 CCU_RESET(RST_USB_PHY1, 0x0cc, 1)
86 CCU_RESET(RST_USB_HSIC, 0x0cc, 2)
88 CCU_RESET(RST_BUS_MIPI_DSI, 0x2c0, 1)
89 CCU_RESET(RST_BUS_CE, 0x2c0, 5)
90 CCU_RESET(RST_BUS_DMA, 0x2c0, 6)
91 CCU_RESET(RST_BUS_MMC0, 0x2c0, 8)
92 CCU_RESET(RST_BUS_MMC1, 0x2c0, 9)
93 CCU_RESET(RST_BUS_MMC2, 0x2c0, 10)
[all …]
H A Dccu_a83t.c52 #define CLK_PLL_C0CPUX 0
80 CCU_RESET(RST_USB_PHY0, 0xcc, 0)
81 CCU_RESET(RST_USB_PHY1, 0xcc, 1)
82 CCU_RESET(RST_USB_HSIC, 0xcc, 2)
84 CCU_RESET(RST_DRAM, 0xf4, 31)
85 CCU_RESET(RST_MBUS, 0xfc, 31)
87 CCU_RESET(RST_BUS_MIPI_DSI, 0x2c0, 1)
88 CCU_RESET(RST_BUS_SS, 0x2c0, 5)
89 CCU_RESET(RST_BUS_DMA, 0x2c0, 6)
90 CCU_RESET(RST_BUS_MMC0, 0x2c0, 8)
[all …]
H A Dccu_a31.c51 #define CLK_PLL_CPU 0
83 CCU_RESET(RST_USB_PHY0, 0xcc, 0)
84 CCU_RESET(RST_USB_PHY1, 0xcc, 1)
85 CCU_RESET(RST_USB_PHY2, 0xcc, 2)
87 CCU_RESET(RST_AHB1_MIPI_DSI, 0x2c0, 1)
88 CCU_RESET(RST_AHB1_SS, 0x2c0, 5)
89 CCU_RESET(RST_AHB1_DMA, 0x2c0, 6)
90 CCU_RESET(RST_AHB1_MMC0, 0x2c0, 8)
91 CCU_RESET(RST_AHB1_MMC1, 0x2c0, 9)
92 CCU_RESET(RST_AHB1_MMC2, 0x2c0, 10)
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
H A Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
H A Dimx35-pinfunc.h13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0
14 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0
15 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0
16 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0
17 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0
18 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0
19 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0
20 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0
21 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0
22 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0
[all …]
H A Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
H A Dimxrt1170-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
[all …]
H A Dimx6q-pinfunc.h13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
[all …]
H A Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dmarvell,mpic.yaml58 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
H A Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
H A Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
/freebsd/sys/dev/qat/qat_hw/qat_4xxx/
H A Dadf_4xxx_hw_data.h8 #define DEFAULT_4XXX_ASYM_AE_MASK 0x03
9 #define DEFAULT_401XX_ASYM_AE_MASK 0x3F
12 #define ADF_4XXX_SRAM_BAR 0
16 #define ADF_4XXX_TX_RINGS_MASK 0x1
19 #define ADF_4XXX_BAR_MASK (BIT(0) | BIT(2) | BIT(4))
26 #define ADF_4XXX_FUSECTL0_OFFSET (0x2C8)
27 #define ADF_4XXX_FUSECTL1_OFFSET (0x2CC)
28 #define ADF_4XXX_FUSECTL2_OFFSET (0x2D0)
29 #define ADF_4XXX_FUSECTL3_OFFSET (0x2D4)
30 #define ADF_4XXX_FUSECTL4_OFFSET (0x2D8)
[all …]
/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dmvebu-mbus.txt65 pcie-mem-aperture = <0xe0000000 0x8000000>;
66 pcie-io-aperture = <0xe8000000 0x100000>;
73 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
87 0xSIAA0000 0x00oooooo
91 S = 0x0 for a MBus valid window
92 S = 0xf for a non-valid window (see below)
94 If S = 0x0, then:
99 If S = 0xf, then:
105 (S = 0x0), an address decoding window is allocated. On the other side,
106 entries for translation that do not correspond to valid windows (S = 0xf)
[all …]
/freebsd/sys/dev/nfe/
H A Dif_nfereg.h45 #define NFE_IRQ_STATUS 0x000
46 #define NFE_IRQ_MASK 0x004
47 #define NFE_SETUP_R6 0x008
48 #define NFE_IMTIMER 0x00c
49 #define NFE_MSI_MAP0 0x020
50 #define NFE_MSI_MAP1 0x024
51 #define NFE_MSI_IRQ_MASK 0x030
52 #define NFE_MAC_RESET 0x03c
53 #define NFE_MISC1 0x080
54 #define NFE_TX_CTL 0x084
[all …]
/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-xp.dtsi35 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
41 reg = <0x1400 0x500>;
46 reg = <0x08000 0x1000>;
47 cache-id-part = <0x100>;
55 pinctrl-0 = <&uart2_pins>;
57 reg = <0x12200 0x100>;
61 clocks = <&coreclk 0>;
67 pinctrl-0 = <&uart3_pins>;
69 reg = <0x12300 0x100>;
73 clocks = <&coreclk 0>;
[all …]
H A Darmada-xp-98dx3236.dtsi28 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
35 clocks = <&cpuclk 0>;
43 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
44 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
45 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
46 MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
47 MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
51 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
[all …]
/freebsd/sys/dev/sk/
H A Dxmaciireg.h43 #define XM_DEVICEID 0x00E0AE20
44 #define XM_XAQTI_OUI 0x00E0AE
46 #define XM_XMAC_REV(x) (((x) & 0x000000E0) >> 5)
48 #define XM_XMAC_REV_B2 0x0
49 #define XM_XMAC_REV_C1 0x1
51 #define XM_MMUCMD 0x0000
52 #define XM_POFF 0x0008
53 #define XM_BURST 0x000C
54 #define XM_VLAN_TAGLEV1 0x0010
55 #define XM_VLAN_TAGLEV2 0x0014
[all …]
/freebsd/sys/dev/ffec/
H A Dif_ffecreg.h41 #define FEC_IER_REG 0x0004
42 #define FEC_IEM_REG 0x0008
61 #define FEC_RDAR_REG 0x0010
64 #define FEC_TDAR_REG 0x0014
67 #define FEC_ECR_REG 0x0024
76 #define FEC_ECR_RESET (1 << 0)
78 #define FEC_MMFR_REG 0x0040
80 #define FEC_MMFR_ST_VALUE (0x01 << FEC_MMFR_ST_SHIFT)
82 #define FEC_MMFR_OP_WRITE (0x01 << FEC_MMFR_OP_SHIFT)
83 #define FEC_MMFR_OP_READ (0x02 << FEC_MMFR_OP_SHIFT)
[all …]
/freebsd/contrib/expat/tests/
H A Dcommon.c112 = "<documentwitharidiculouslylongelementnametotease" /* 0x030 */
113 "aparticularcorneroftheallocationinXML_GetBuffers" /* 0x060 */
114 "othatwecanimprovethecoverageyetagain012345678901" /* 0x090 */
115 "123456789abcdef0123456789abcdef0123456789abcdef0" /* 0x0c0 */
116 "123456789abcdef0123456789abcdef0123456789abcdef0" /* 0x0f0 */
117 "123456789abcdef0123456789abcdef0123456789abcdef0" /* 0x120 */
118 "123456789abcdef0123456789abcdef0123456789abcdef0" /* 0x150 */
119 "123456789abcdef0123456789abcdef0123456789abcdef0" /* 0x180 */
120 "123456789abcdef0123456789abcdef0123456789abcdef0" /* 0x1b0 */
121 "123456789abcdef0123456789abcdef0123456789abcdef0" /* 0x1e
[all...]
/freebsd/sys/powerpc/pseries/
H A Dphyp-hvcall.h37 #define H_SUCCESS 0
172 #define H_SET_MODE_RSRC_CIABR 0x1 /* All versions */
173 #define H_SET_MODE_RSRC_DAWR0 0x2 /* All versions */
174 #define H_SET_MODE_RSRC_INTR_TRANS_MODE 0x3 /* All versions */
175 #define H_SET_MODE_RSRC_ILE 0x4 /* PAPR 2.8 / ISA 2.07 */
176 #define H_SET_MODE_RSRC_DAWR1 0x5 /* ISA 3.1 Future support */
179 #define PROC_TABLE_OP_MASK 0x18
180 #define PROC_TABLE_DEREG 0x10
181 #define PROC_TABLE_NEW 0x18
182 #define PROC_TABLE_TYPE_MASK 0x06
[all …]
/freebsd/crypto/heimdal/lib/wind/
H A Dbidi_table.c9 {0x5be, 1},
10 {0x5c0, 1},
11 {0x5c3, 1},
12 {0x5d0, 0x1b},
13 {0x5f0, 0x5},
14 {0x61b, 1},
15 {0x61f, 1},
16 {0x621, 0x1a},
17 {0x640, 0xb},
18 {0x66d, 0x3},
[all …]

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