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/linux/Documentation/devicetree/bindings/watchdog/
H A Dmpc8xxx-wdt.txt10 On the 83xx, "Watchdog Timer Registers" area: <0x200 0x100>
11 On the 86xx, "Watchdog Timer Registers" area: <0xe4000 0x100>
12 On the 8xx, "General System Interface Unit" area: <0x0 0x10>
17 On the 83xx, it is located at offset 0x910
18 On the 86xx, it is located at offset 0xe0094
19 On the 8xx, it is located at offset 0x288
22 WDT: watchdog@0 {
24 reg = <0x0 0x10 0x288 0x4>;
/linux/drivers/media/platform/mediatek/mdp3/
H A Dmdp_reg_rdma.h10 #define MDP_RDMA_EN 0x000
11 #define MDP_RDMA_RESET 0x008
12 #define MDP_RDMA_CON 0x020
13 #define MDP_RDMA_GMCIF_CON 0x028
14 #define MDP_RDMA_SRC_CON 0x030
15 #define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
16 #define MDP_RDMA_MF_BKGD_SIZE_IN_PXL 0x068
17 #define MDP_RDMA_MF_SRC_SIZE 0x070
18 #define MDP_RDMA_MF_CLIP_SIZE 0x078
19 #define MDP_RDMA_MF_OFFSET_1 0x080
[all …]
/linux/drivers/clk/meson/
H A Daxg.h19 #define HHI_GP0_PLL_CNTL 0x40
20 #define HHI_GP0_PLL_CNTL2 0x44
21 #define HHI_GP0_PLL_CNTL3 0x48
22 #define HHI_GP0_PLL_CNTL4 0x4c
23 #define HHI_GP0_PLL_CNTL5 0x50
24 #define HHI_GP0_PLL_STS 0x54
25 #define HHI_GP0_PLL_CNTL1 0x58
26 #define HHI_HIFI_PLL_CNTL 0x80
27 #define HHI_HIFI_PLL_CNTL2 0x84
28 #define HHI_HIFI_PLL_CNTL3 0x88
[all …]
H A Dg12a.h20 #define HHI_MIPI_CNTL0 0x000
21 #define HHI_MIPI_CNTL1 0x004
22 #define HHI_MIPI_CNTL2 0x008
23 #define HHI_MIPI_STS 0x00C
24 #define HHI_GP0_PLL_CNTL0 0x040
25 #define HHI_GP0_PLL_CNTL1 0x044
26 #define HHI_GP0_PLL_CNTL2 0x048
27 #define HHI_GP0_PLL_CNTL3 0x04C
28 #define HHI_GP0_PLL_CNTL4 0x050
29 #define HHI_GP0_PLL_CNTL5 0x054
[all …]
H A Dmeson8b.h16 * Register offsets from the HardKernel[0] data sheet are listed in comment
20 * [0] https://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
22 #define HHI_GP_PLL_CNTL 0x40 /* 0x10 offset in data sheet */
23 #define HHI_GP_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */
24 #define HHI_GP_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */
25 #define HHI_GP_PLL_CNTL4 0x4C /* 0x13 offset in data sheet */
26 #define HHI_GP_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */
27 #define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */
28 #define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
29 #define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */
[all …]
/linux/Documentation/userspace-api/media/v4l/
H A Drw.rst28 $ vidctrl /dev/video --input=0 --format=YUYV --size=352x288
/linux/drivers/media/usb/gspca/stv06xx/
H A Dstv06xx.h25 #define STV_ISOC_ENDPOINT_ADDR 0x81
27 #define STV_R 0x0509
29 #define STV_REG23 0x0423
32 #define STV_I2C_PARTNER 0x1420
33 #define STV_I2C_VAL_REG_VAL_PAIRS_MIN1 0x1421
34 #define STV_I2C_READ_WRITE_TOGGLE 0x1422
35 #define STV_I2C_FLUSH 0x1423
36 #define STV_I2C_SUCC_READ_REG_VALS 0x1424
38 #define STV_ISO_ENABLE 0x1440
39 #define STV_SCAN_RATE 0x1443
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/linux/arch/s390/include/uapi/asm/
H A Dsie.h6 { 0x10, "DIAG (0x10) release pages" }, \
7 { 0x44, "DIAG (0x44) time slice end" }, \
8 { 0x9c, "DIAG (0x9c) time slice end directed" }, \
9 { 0x204, "DIAG (0x204) logical-cpu utilization" }, \
10 { 0x258, "DIAG (0x258) page-reference services" }, \
11 { 0x288, "DIAG (0x288) watchdog functions" }, \
12 { 0x308, "DIAG (0x308) ipl functions" }, \
13 { 0x500, "DIAG (0x500) KVM virtio functions" }, \
14 { 0x501, "DIAG (0x501) KVM breakpoint" }
17 { 0x01, "SIGP sense" }, \
[all …]
/linux/tools/arch/s390/include/uapi/asm/
H A Dsie.h6 { 0x10, "DIAG (0x10) release pages" }, \
7 { 0x44, "DIAG (0x44) time slice end" }, \
8 { 0x9c, "DIAG (0x9c) time slice end directed" }, \
9 { 0x204, "DIAG (0x204) logical-cpu utilization" }, \
10 { 0x258, "DIAG (0x258) page-reference services" }, \
11 { 0x288, "DIAG (0x288) watchdog functions" }, \
12 { 0x308, "DIAG (0x308) ipl functions" }, \
13 { 0x500, "DIAG (0x500) KVM virtio functions" }, \
14 { 0x501, "DIAG (0x501) KVM breakpoint" }
17 { 0x01, "SIGP sense" }, \
[all …]
/linux/drivers/media/usb/gspca/
H A Dtv8532.c32 .priv = 0},
36 #define R00_PART_CONTROL 0x00
37 #define LATENT_CHANGE 0x80
38 #define EXPO_CHANGE 0x04
39 #define R01_TIMING_CONTROL_LOW 0x01
40 #define CMD_EEprom_Open 0x30
41 #define CMD_EEprom_Close 0x29
42 #define R03_TABLE_ADDR 0x03
43 #define R04_WTRAM_DATA_L 0x04
44 #define R05_WTRAM_DATA_M 0x05
[all …]
H A Dpac207.c27 #define PAC207_BRIGHTNESS_MIN 0
30 #define PAC207_BRIGHTNESS_REG 0x08
35 #define PAC207_EXPOSURE_REG 0x02
37 #define PAC207_GAIN_MIN 0
40 #define PAC207_GAIN_REG 0x0e
76 .priv = 0},
80 {0x10, 0x12, 0x0d, 0x12, 0x0c, 0x01, 0x29, 0x84},
81 {0x49, 0x64, 0x64, 0x64, 0x04, 0x10, 0xf0, 0x30},
82 {0x00, 0x00, 0x00, 0x70, 0xa0, 0xf8, 0x00, 0x00},
83 {0x32, 0x00, 0x96, 0x00, 0xa2, 0x02, 0xaf, 0x00},
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
H A Dimx35-pinfunc.h13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0
14 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0
15 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0
16 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0
17 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0
18 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0
19 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0
20 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0
21 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0
22 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0
[all …]
/linux/tools/perf/arch/powerpc/util/
H A Dbook3s_hcalls.h9 {0x4, "H_REMOVE"}, \
10 {0x8, "H_ENTER"}, \
11 {0xc, "H_READ"}, \
12 {0x10, "H_CLEAR_MOD"}, \
13 {0x14, "H_CLEAR_REF"}, \
14 {0x18, "H_PROTECT"}, \
15 {0x1c, "H_GET_TCE"}, \
16 {0x20, "H_PUT_TCE"}, \
17 {0x24, "H_SET_SPRG0"}, \
18 {0x28, "H_SET_DABR"}, \
[all …]
/linux/drivers/gpu/drm/xe/
H A Dxe_lrc.c31 #define LRC_VALID BIT_ULL(0)
92 * [5:0]: Number of NOPs or registers to set values to in case of
97 * is used for offsets smaller than 0x200 while the latter is for values bigger
102 * [6:0]: Register offset, without considering the engine base.
113 #define POSTED BIT(0) in set_offsets()
114 #define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200)) in set_offsets()
116 (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x10000)), \ in set_offsets()
117 (((x) >> 2) & 0x7f) in set_offsets()
130 count = *data & 0x3f; in set_offsets()
142 u32 offset = 0; in set_offsets()
[all …]
/linux/drivers/media/pci/intel/ipu6/
H A Dipu6-platform-isys-csi2-reg.h9 #define CSI_REG_BASE 0x220000
10 #define CSI_REG_PORT_BASE(id) (CSI_REG_BASE + (id) * 0x1000)
13 #define CSI_REG_PORT_GPREG_SRST 0x0
14 #define CSI_REG_PORT_GPREG_CSI2_SLV_REG_SRST 0x4
15 #define CSI_REG_PORT_GPREG_CSI2_PORT_CONTROL 0x8
24 #define CSI_PORT_REG_BASE_IRQ_CSI 0x80
25 #define CSI_PORT_REG_BASE_IRQ_CSI_SYNC 0xA0
26 #define CSI_PORT_REG_BASE_IRQ_S2M_SIDS0TOS7 0xC0
27 #define CSI_PORT_REG_BASE_IRQ_S2M_SIDS8TOS15 0xE0
29 #define CSI_PORT_REG_BASE_IRQ_EDGE_OFFSET 0x0
[all …]
/linux/drivers/gpu/drm/bridge/
H A Dnwl-dsi.h12 #define NWL_DSI_CFG_NUM_LANES 0x0
13 #define NWL_DSI_CFG_NONCONTINUOUS_CLK 0x4
14 #define NWL_DSI_CFG_T_PRE 0x8
15 #define NWL_DSI_CFG_T_POST 0xc
16 #define NWL_DSI_CFG_TX_GAP 0x10
17 #define NWL_DSI_CFG_AUTOINSERT_EOTP 0x14
18 #define NWL_DSI_CFG_EXTRA_CMDS_AFTER_EOTP 0x18
19 #define NWL_DSI_CFG_HTX_TO_COUNT 0x1c
20 #define NWL_DSI_CFG_LRX_H_TO_COUNT 0x20
21 #define NWL_DSI_CFG_BTA_H_TO_COUNT 0x24
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mt6735-apmixedsys.c14 #define AP_PLL_CON_5 0x014
15 #define ARMPLL_CON0 0x200
16 #define ARMPLL_CON1 0x204
17 #define ARMPLL_PWR_CON0 0x20c
18 #define MAINPLL_CON0 0x210
19 #define MAINPLL_CON1 0x214
20 #define MAINPLL_PWR_CON0 0x21c
21 #define UNIVPLL_CON0 0x220
22 #define UNIVPLL_CON1 0x224
23 #define UNIVPLL_PWR_CON0 0x22c
[all …]
/linux/drivers/gpu/drm/rockchip/
H A Drk3066_hdmi.h10 #define GRF_SOC_CON0 0x150
13 #define DDC_SEGMENT_ADDR 0x30
15 #define HDMI_MAXIMUM_INFO_FRAME_SIZE 0x11
17 #define N_32K 0x1000
18 #define N_441K 0x1880
19 #define N_882K 0x3100
20 #define N_1764K 0x6200
21 #define N_48K 0x1800
22 #define N_96K 0x3000
23 #define N_192K 0x6000
[all …]
/linux/drivers/media/pci/tw68/
H A Dtw68-reg.h23 #define TW68_DMAC 0x000
24 #define TW68_DMAP_SA 0x004
25 #define TW68_DMAP_EXE 0x008
26 #define TW68_DMAP_PP 0x00c
27 #define TW68_VBIC 0x010
28 #define TW68_SBUSC 0x014
29 #define TW68_SBUSSD 0x018
30 #define TW68_INTSTAT 0x01C
31 #define TW68_INTMASK 0x020
32 #define TW68_GPIOC 0x024
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dfsl,imx35-pinctrl.yaml74 PAD_CTL_DRIVE_VOLAGAGE_33 (0 << 13)
78 PAD_CTL_PUS_100K_DOWN (0 << 4)
82 PAD_CTL_ODE_CMOS (0 << 3)
84 PAD_CTL_DSE_NOMINAL (0 << 1)
87 PAD_CTL_SRE_FAST (1 << 0)
88 PAD_CTL_SRE_SLOW (0 << 0)
94 PAD_CTL_PUS_100K_DOWN (0 << 4)
99 PAD_CTL_DSE_LOW (0 << 1)
103 PAD_CTL_SRE_FAST (1 << 0)
104 PAD_CTL_SRE_SLOW (0 << 0)
[all …]
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi4_core.h15 #define HDMI_CORE_SYS_VND_IDL 0x0
16 #define HDMI_CORE_SYS_DEV_IDL 0x8
17 #define HDMI_CORE_SYS_DEV_IDH 0xC
18 #define HDMI_CORE_SYS_DEV_REV 0x10
19 #define HDMI_CORE_SYS_SRST 0x14
20 #define HDMI_CORE_SYS_SYS_CTRL1 0x20
21 #define HDMI_CORE_SYS_SYS_STAT 0x24
22 #define HDMI_CORE_SYS_SYS_CTRL3 0x28
23 #define HDMI_CORE_SYS_DCTL 0x34
24 #define HDMI_CORE_SYS_DE_DLY 0xC8
[all …]
/linux/drivers/gpu/drm/omapdrm/dss/
H A Dhdmi4_core.h15 #define HDMI_CORE_SYS_VND_IDL 0x0
16 #define HDMI_CORE_SYS_DEV_IDL 0x8
17 #define HDMI_CORE_SYS_DEV_IDH 0xC
18 #define HDMI_CORE_SYS_DEV_REV 0x10
19 #define HDMI_CORE_SYS_SRST 0x14
20 #define HDMI_CORE_SYS_SYS_CTRL1 0x20
21 #define HDMI_CORE_SYS_SYS_STAT 0x24
22 #define HDMI_CORE_SYS_SYS_CTRL3 0x28
23 #define HDMI_CORE_SYS_DCTL 0x34
24 #define HDMI_CORE_SYS_DE_DLY 0xC8
[all …]
/linux/arch/arm/mach-s3c/
H A Dregs-gpio-s3c64xx.h19 #define S3C64XX_GPA_BASE S3C64XX_GPIOREG(0x0000)
20 #define S3C64XX_GPB_BASE S3C64XX_GPIOREG(0x0020)
21 #define S3C64XX_GPC_BASE S3C64XX_GPIOREG(0x0040)
22 #define S3C64XX_GPD_BASE S3C64XX_GPIOREG(0x0060)
23 #define S3C64XX_GPE_BASE S3C64XX_GPIOREG(0x0080)
24 #define S3C64XX_GPF_BASE S3C64XX_GPIOREG(0x00A0)
25 #define S3C64XX_GPG_BASE S3C64XX_GPIOREG(0x00C0)
26 #define S3C64XX_GPH_BASE S3C64XX_GPIOREG(0x00E0)
27 #define S3C64XX_GPI_BASE S3C64XX_GPIOREG(0x0100)
28 #define S3C64XX_GPJ_BASE S3C64XX_GPIOREG(0x0120)
[all …]

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