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/linux/sound/soc/intel/atom/sst/
H A Dsst_acpi.c39 #define SST_BYT_IRAM_PHY_START 0xff2c0000
40 #define SST_BYT_IRAM_PHY_END 0xff2d4000
41 #define SST_BYT_DRAM_PHY_START 0xff300000
42 #define SST_BYT_DRAM_PHY_END 0xff320000
43 #define SST_BYT_IMR_VIRT_START 0xc0000000 /* virtual addr in LPE */
44 #define SST_BYT_IMR_VIRT_END 0xc01fffff
45 #define SST_BYT_SHIM_PHY_ADDR 0xff340000
46 #define SST_BYT_MBOX_PHY_ADDR 0xff344000
47 #define SST_BYT_DMA0_PHY_ADDR 0xff298000
48 #define SST_BYT_DMA1_PHY_ADDR 0xff29c00
[all...]
/linux/Documentation/devicetree/bindings/net/
H A Dfsl,fman-muram.yaml37 muram@0 {
39 reg = <0x0 0x28000>;
H A Dfsl,fman.yaml22 FMan block. The offset is 0xc4 from the beginning of the
23 Frame Processing Manager memory map (0xc3000 from the
38 DEVDISR[1] 1 0
43 DCFG_DEVDISR2[6] 1 0
50 DCFG_CCSR_DEVDISR2[24] 1 0
156 reg = <0x400000 0x100000>;
157 ranges = <0 0x400000 0x100000>;
165 fsl,qman-channel-range = <0x40 0xc>;
167 muram@0 {
169 reg = <0x0 0x28000>;
[all …]
/linux/Documentation/devicetree/bindings/interconnect/
H A Dqcom,sm6350-rpmh.yaml107 reg = <0x01500000 0x28000>;
114 reg = <0x01700000 0x1f880>;
/linux/arch/powerpc/include/asm/
H A Dhydra.h30 char Pad1[0x30];
34 char Pad2[0x7fc4];
36 char SCSI_DMA[0x100];
37 char Pad3[0x300];
38 char SCCA_Tx_DMA[0x100];
39 char SCCA_Rx_DMA[0x100];
40 char SCCB_Tx_DMA[0x100];
41 char SCCB_Rx_DMA[0x100];
42 char Pad4[0x7800];
44 char SCSI[0x1000];
[all …]
/linux/arch/mips/dec/prom/
H A Dmemory.c28 #define CHUNK_SIZE 0x400000
33 char old_handler[0x80]; in pmax_setup_memory_region()
37 memcpy(&old_handler, (void *)(CKSEG0 + 0x80), 0x80); in pmax_setup_memory_region()
38 memcpy((void *)(CKSEG0 + 0x80), &genexcept_early, 0x80); in pmax_setup_memory_region()
46 mem_err == 0 && memory_page < (unsigned char *)CKSEG1 + 0x1e00000; in pmax_setup_memory_region()
50 memcpy((void *)(CKSEG0 + 0x80), &old_handler, 0x80); in pmax_setup_memory_region()
52 memblock_add(0, (unsigned long)memory_page - CKSEG1 - CHUNK_SIZE); in pmax_setup_memory_region()
62 unsigned long mem_start = 0, mem_size = 0; in rex_setup_memory_region()
66 bm = (memmap *)CKSEG0ADDR(0x28000); in rex_setup_memory_region()
70 for (i = 0; i < bitmap_size; i++) { in rex_setup_memory_region()
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-fman-0.dtsi2 * QorIQ FMan device tree stub [ controller @ offset 0x400000 ]
38 cell-index = <0>;
40 ranges = <0 0x400000 0xfe000>;
41 reg = <0x400000 0xfe000>;
42 interrupts = <96 2 0 0>, <16 2 1 1>;
43 clocks = <&clockgen 3 0>;
45 fsl,qman-channel-range = <0x40 0xc>;
48 muram@0 {
50 reg = <0x0 0x28000>;
54 cell-index = <0x1>;
[all …]
H A Dqoriq-fman-1.dtsi2 * QorIQ FMan device tree stub [ controller @ offset 0x500000 ]
40 ranges = <0 0x500000 0xfe000>;
41 reg = <0x500000 0xfe000>;
42 interrupts = <97 2 0 0>, <16 2 1 0>;
45 fsl,qman-channel-range = <0x60 0xc>;
48 muram@0 {
50 reg = <0x0 0x28000>;
54 cell-index = <0x1>;
56 reg = <0x81000 0x1000>;
60 cell-index = <0x2>;
[all …]
H A Db4si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x200000 */
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
66 pcie@0 {
71 reg = <0 0 0 0 0>;
72 interrupts = <20 2 0 0>;
[all …]
H A Dt2081si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
66 pcie@0 {
67 reg = <0 0 0 0 0>;
[all …]
/linux/Documentation/devicetree/bindings/remoteproc/
H A Dqcom,sc7280-adsp-pil.yaml153 reg = <0x03000000 0x5000>,
154 <0x0355b000 0x10>;
157 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
176 qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>;
180 qcom,smem-states = <&adsp_smp2p_out 0>;
/linux/drivers/crypto/intel/iaa/
H A Diaa_crypto_comp_fixed.c11 0x40030, 0x40031, 0x40032, 0x40033, 0x40034, 0x40035, 0x40036, 0x40037,
12 0x40038, 0x40039, 0x4003A, 0x4003B, 0x4003C, 0x4003D, 0x4003E, 0x4003F,
13 0x40040, 0x40041, 0x40042, 0x40043, 0x40044, 0x40045, 0x40046, 0x40047,
14 0x40048, 0x40049, 0x4004A, 0x4004B, 0x4004C, 0x4004D, 0x4004E, 0x4004F,
15 0x40050, 0x40051, 0x40052, 0x40053, 0x40054, 0x40055, 0x40056, 0x40057,
16 0x40058, 0x40059, 0x4005A, 0x4005B, 0x4005C, 0x4005D, 0x4005E, 0x4005F,
17 0x40060, 0x40061, 0x40062, 0x40063, 0x40064, 0x40065, 0x40066, 0x40067,
18 0x40068, 0x40069, 0x4006A, 0x4006B, 0x4006C, 0x4006D, 0x4006E, 0x4006F,
19 0x40070, 0x40071, 0x40072, 0x40073, 0x40074, 0x40075, 0x40076, 0x40077,
20 0x40078, 0x40079, 0x4007A, 0x4007B, 0x4007C, 0x4007D, 0x4007E, 0x4007F,
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dat91sam9261.dtsi38 #size-cells = <0>;
40 cpu@0 {
43 reg = <0>;
49 reg = <0x20000000 0x08000000>;
55 #clock-cells = <0>;
56 clock-frequency = <0>;
61 #clock-cells = <0>;
62 clock-frequency = <0>;
68 reg = <0x00300000 0x28000>;
71 ranges = <0 0x00300000 0x28000>;
[all …]
/linux/drivers/net/ethernet/hisilicon/hns3/hns3vf/
H A Dhclgevf_main.h20 #define HCLGEVF_MISC_VECTOR_NUM 0
22 #define HCLGEVF_INVALID_VPORT 0xffff
32 #define HCLGEVF_VECTOR_REG_BASE 0x20000
33 #define HCLGEVF_MISC_VECTOR_REG_BASE 0x20400
34 #define HCLGEVF_VECTOR_REG_OFFSET 0x4
35 #define HCLGEVF_VECTOR_VF_OFFSET 0x100000
38 #define HCLGEVF_GRO_EN_REG 0x28000
39 #define HCLGEVF_RXD_ADV_LAYOUT_EN_REG 0x28008
42 #define HCLGEVF_RING_RX_ADDR_L_REG 0x80000
43 #define HCLGEVF_RING_RX_ADDR_H_REG 0x80004
[all …]
/linux/Documentation/sound/hd-audio/
H A Dintel-multi-link.rst16 External HDAudio codecs are handled with link #0, while iDISP codec
20 LCAP.ALT=0x0 - since the ALT bit was previously reserved, this is a
33 | ML cap #0 |
38 +--> 0x0 +---------------+ LCAP
39 | ALT=0 |
54 0x4 +---------------+ LCTL
64 0x8 +---------------+ LOSIDV
72 0xC +---------------+ LSDIID
84 LEPTR.ID=0.
98 ML address, with a default value of 0x30000.
[all …]
/linux/sound/pci/au88x0/
H A Dau8810.h11 #define NR_ADB 0x10
12 #define NR_WT 0x00
13 #define NR_SRC 0x10
14 #define NR_A3D 0x10
15 #define NR_MIXIN 0x20
16 #define NR_MIXOUT 0x10
20 #define VORTEX_ADBDMA_STAT 0x27e00 /* read only, subbuffer, DMA pos */
21 #define POS_MASK 0x00000fff
22 #define POS_SHIFT 0x0
23 #define ADB_SUBBUF_MASK 0x00003000 /* ADB only. */
[all …]
H A Dau8830.h18 #define NR_ADB 0x20
19 #define NR_SRC 0x10
20 #define NR_A3D 0x10
21 #define NR_MIXIN 0x20
22 #define NR_MIXOUT 0x10
23 #define NR_WT 0x40
26 #define VORTEX_ADBDMA_STAT 0x27e00 /* read only, subbuffer, DMA pos */
27 #define POS_MASK 0x00000fff
28 #define POS_SHIFT 0x0
29 #define ADB_SUBBUF_MASK 0x00003000 /* ADB only. */
[all …]
/linux/arch/powerpc/boot/dts/
H A Dmpc885ads.dts19 #size-cells = <0>;
21 PowerPC,885@0 {
23 reg = <0x0>;
28 timebase-frequency = <0>;
29 bus-frequency = <0>;
30 clock-frequency = <0>;
38 reg = <0x0 0x0>;
45 reg = <0xff000100 0x40>;
48 0x0 0x0 0xfe000000 0x800000
49 0x1 0x0 0xff080000 0x8000
[all …]
/linux/drivers/media/pci/netup_unidvb/
H A Dnetup_unidvb_ci.c22 /* CI slot 0 base address */
23 #define CAM0_CONFIG 0x0
24 #define CAM0_IO 0x8000
25 #define CAM0_MEM 0x10000
28 #define CAM1_CONFIG 0x20000
29 #define CAM1_IO 0x28000
30 #define CAM1_MEM 0x30000
33 #define CAM_CTRLSTAT_READ_SET 0x4980
34 #define CAM_CTRLSTAT_CLR 0x4982
36 #define BIT_CAM_STCHG (1<<0)
[all …]
/linux/drivers/net/wireless/ti/wl1251/
H A Dwl1251.h21 DEBUG_NONE = 0,
22 DEBUG_IRQ = BIT(0),
36 DEBUG_ALL = ~0,
59 } while (0)
68 0); \
69 } while (0)
79 } while (0)
410 #define WL1251_DEFAULT_CHANNEL 0
414 #define CHIP_ID_1251_PG10 (0x7010101)
415 #define CHIP_ID_1251_PG11 (0x7020101)
[all …]
/linux/include/uapi/misc/
H A Dxilinx_sdfec.h17 #define XSDFEC_LDPC_SC_TABLE_ADDR_BASE (0x10000)
18 #define XSDFEC_LDPC_SC_TABLE_ADDR_HIGH (0x10400)
19 #define XSDFEC_LDPC_LA_TABLE_ADDR_BASE (0x18000)
20 #define XSDFEC_LDPC_LA_TABLE_ADDR_HIGH (0x19000)
21 #define XSDFEC_LDPC_QC_TABLE_ADDR_BASE (0x20000)
22 #define XSDFEC_LDPC_QC_TABLE_ADDR_HIGH (0x28000)
42 XSDFEC_TURBO_CODE = 0,
55 XSDFEC_MAINTAIN_ORDER = 0,
70 XSDFEC_MAX_SCALE = 0,
86 XSDFEC_INIT = 0,
[all …]
/linux/drivers/net/dsa/
H A Dbcm_sf2_regs.h13 REG_SWITCH_CNTRL = 0,
36 #define MDIO_MASTER_SEL (1 << 0)
39 #define SF2_REV_MASK 0xffff
41 #define SWITCH_TOP_REV_MASK 0xffff
44 #define PHY_REVISION_MASK 0xffff
47 #define IDDQ_BIAS (1 << 0)
54 #define PHY_PHYAD_MASK 0x1F
57 #define CROSSBAR_BCM4908_INT_P7 0
59 #define CROSSBAR_BCM4908_EXT_SERDES 0
64 #define LED_CNTRL_NO_LINK_ENCODE_SHIFT 0
[all …]
/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_8_1_sm8450.h12 .max_mixer_blendstages = 0xb,
23 .base = 0x0, .len = 0x494,
25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
H A Ddpu_9_1_sar2130p.h12 .max_mixer_blendstages = 0xb,
23 .base = 0, .len = 0x494,
25 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
32 .base = 0x15000, .len = 0x290,
36 .base = 0x16000, .len = 0x290,
40 .base = 0x17000, .len = 0x290,
44 .base = 0x18000, .len = 0x290,
48 .base = 0x19000, .len = 0x290,
52 .base = 0x1a000, .len = 0x290,
60 .base = 0x4000, .len = 0x344,
[all …]
H A Ddpu_9_0_sm8550.h12 .max_mixer_blendstages = 0xb,
23 .base = 0, .len = 0x494,
25 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
32 .base = 0x15000, .len = 0x290,
36 .base = 0x16000, .len = 0x290,
40 .base = 0x17000, .len = 0x290,
44 .base = 0x18000, .len = 0x290,
48 .base = 0x19000, .len = 0x290,
52 .base = 0x1a000, .len = 0x290,
60 .base = 0x4000, .len = 0x344,
[all …]

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