Lines Matching +full:0 +full:x28000

20 #define HCLGEVF_MISC_VECTOR_NUM		0
22 #define HCLGEVF_INVALID_VPORT		0xffff
32 #define HCLGEVF_VECTOR_REG_BASE		0x20000
33 #define HCLGEVF_MISC_VECTOR_REG_BASE	0x20400
34 #define HCLGEVF_VECTOR_REG_OFFSET	0x4
35 #define HCLGEVF_VECTOR_VF_OFFSET		0x100000
38 #define HCLGEVF_GRO_EN_REG			0x28000
39 #define HCLGEVF_RXD_ADV_LAYOUT_EN_REG		0x28008
42 #define HCLGEVF_RING_RX_ADDR_L_REG		0x80000
43 #define HCLGEVF_RING_RX_ADDR_H_REG		0x80004
44 #define HCLGEVF_RING_RX_BD_NUM_REG		0x80008
45 #define HCLGEVF_RING_RX_BD_LENGTH_REG		0x8000C
46 #define HCLGEVF_RING_RX_MERGE_EN_REG		0x80014
47 #define HCLGEVF_RING_RX_TAIL_REG		0x80018
48 #define HCLGEVF_RING_RX_HEAD_REG		0x8001C
49 #define HCLGEVF_RING_RX_FBD_NUM_REG		0x80020
50 #define HCLGEVF_RING_RX_OFFSET_REG		0x80024
51 #define HCLGEVF_RING_RX_FBD_OFFSET_REG		0x80028
52 #define HCLGEVF_RING_RX_STASH_REG		0x80030
53 #define HCLGEVF_RING_RX_BD_ERR_REG		0x80034
54 #define HCLGEVF_RING_TX_ADDR_L_REG		0x80040
55 #define HCLGEVF_RING_TX_ADDR_H_REG		0x80044
56 #define HCLGEVF_RING_TX_BD_NUM_REG		0x80048
57 #define HCLGEVF_RING_TX_PRIORITY_REG		0x8004C
58 #define HCLGEVF_RING_TX_TC_REG			0x80050
59 #define HCLGEVF_RING_TX_MERGE_EN_REG		0x80054
60 #define HCLGEVF_RING_TX_TAIL_REG		0x80058
61 #define HCLGEVF_RING_TX_HEAD_REG		0x8005C
62 #define HCLGEVF_RING_TX_FBD_NUM_REG		0x80060
63 #define HCLGEVF_RING_TX_OFFSET_REG		0x80064
64 #define HCLGEVF_RING_TX_EBD_NUM_REG		0x80068
65 #define HCLGEVF_RING_TX_EBD_OFFSET_REG		0x80070
66 #define HCLGEVF_RING_TX_BD_ERR_REG		0x80074
67 #define HCLGEVF_RING_EN_REG			0x80090
70 #define HCLGEVF_TQP_INTR_CTRL_REG		0x20000
71 #define HCLGEVF_TQP_INTR_GL0_REG		0x20100
72 #define HCLGEVF_TQP_INTR_GL1_REG		0x20200
73 #define HCLGEVF_TQP_INTR_GL2_REG		0x20300
74 #define HCLGEVF_TQP_INTR_RL_REG			0x20900
83 #define HCLGEVF_RST_ING			0x20C00
84 #define HCLGEVF_FUN_RST_ING_BIT		BIT(0)
92 #define HCLGEVF_VF_RST_ING		0x07008
99 #define HCLGEVF_TQP_MEM_SIZE		0x10000
224 #define HCLGEVF_RESET_REQUESTED		0