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/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap2430.dtsi18 ranges = <0 0x49000000 0x31000>;
22 reg = <0x6000 0x1000>;
26 #size-cells = <0>;
35 reg = <0x2000 0x1000>;
39 ranges = <0 0x2000 0x1000>;
44 reg = <0x30 0x0154>;
46 #size-cells = <0>;
49 pinctrl-single,function-mask = <0x3f>;
55 reg = <0x270 0x240>;
58 ranges = <0 0x270 0x240>;
[all …]
H A Domap2420.dtsi18 ranges = <0 0x48000000 0x100000>;
22 reg = <0x8000 0x1000>;
26 #size-cells = <0>;
33 scm: scm@0 {
35 reg = <0x0 0x1000>;
39 ranges = <0 0x0 0x1000>;
44 reg = <0x30 0x0113>;
46 #size-cells = <0>;
49 pinctrl-single,function-mask = <0x3f>;
54 reg = <0x270 0x100>;
[all …]
H A Domap3.dtsi34 #size-cells = <0>;
36 cpu@0 {
39 reg = <0x0>;
50 reg = <0x54000000 0x800000>;
85 reg = <0x68000000 0x10000>;
96 ranges = <0 0x48000000 0x1000000>;
100 reg = <0x2000 0x2000>;
103 ranges = <0 0x2000 0x2000>;
108 reg = <0x30 0x238>;
110 #size-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/omap/
H A Dctrl.txt41 reg = <0x2000 0x2000>;
44 ranges = <0 0x2000 0x2000>;
49 reg = <0x30 0x230>;
51 #size-cells = <0>;
55 pinctrl-single,function-mask = <0xff1f>;
60 reg = <0x27
[all...]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
H A Dimx35-pinfunc.h13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0
14 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0
15 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0
16 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0
17 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0
18 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0
19 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0
20 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0
21 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0
22 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0
[all …]
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimx6q-pinfunc.h13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
[all …]
H A Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
H A Dimx51-pinfunc.h13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
[all …]
H A Dimxrt1170-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
[all …]
H A Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/apple/
H A Dapple,pmgr.yaml20 pattern: "^power-management@[0-9a-f]+$"
42 "power-controller@[0-9a-f]+$":
64 reg = <0x2 0x3b700000 0x0 0x14000>;
68 reg = <0x1c0 8>;
69 #power-domain-cells = <0>;
70 #reset-cells = <0>;
77 reg = <0x220 8>;
78 #power-domain-cells = <0>;
79 #reset-cells = <0>;
86 reg = <0x270 8>;
[all …]
/freebsd/usr.sbin/cxgbetool/
H A Dreg_defs_t4vf.c7 { "SGE_KDOORBELL", 0x000, 0 },
10 { "PIDX", 0, 14 },
11 { "SGE_GTS", 0x004, 0 },
15 { "CIDXInc", 0, 12 },
17 { NULL, 0, 0 }
21 { "SGE_VF_KDOORBELL", 0x000, 0 },
25 { "PIDX", 0, 13 },
26 { "SGE_VF_GTS", 0x004, 0 },
30 { "CIDXInc", 0, 12 },
32 { NULL, 0, 0 }
[all …]
/freebsd/sys/dev/bhnd/cores/pcie2/
H A Dbhnd_pcie2_reg.h31 #define BHND_PCIE2_DMA64_TRANSLATION 0x8000000000000000 /**< PCIe-Gen2 DMA64 address translation */
32 #define BHND_PCIE2_DMA64_MASK 0xc000000000000000 /**< PCIe-Gen2 DMA64 translation mask */
38 #define BHND_PCIE2_CLK_CONTROL 0x000
40 #define BHND_PCIE2_RC_PM_CONTROL 0x004
41 #define BHND_PCIE2_RC_PM_STATUS 0x008
42 #define BHND_PCIE2_EP_PM_CONTROL 0x00C
43 #define BHND_PCIE2_EP_PM_STATUS 0x010
44 #define BHND_PCIE2_EP_LTR_CONTROL 0x014
45 #define BHND_PCIE2_EP_LTR_STATUS 0x018
46 #define BHND_PCIE2_EP_OBFF_STATUS 0x01C
[all …]
/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_pcie_regs.h54 #define AL_PCIE_AXI_REGS_OFFSET 0x0
55 #define AL_PCIE_REV_1_2_APP_REGS_OFFSET 0x1000
56 #define AL_PCIE_REV_3_APP_REGS_OFFSET 0x2000
57 #define AL_PCIE_REV_1_2_CORE_CONF_BASE_OFFSET 0x2000
58 #define AL_PCIE_REV_3_CORE_CONF_BASE_OFFSET 0x10000
80 uint32_t rsrvd[(0x270 - 0x224) >> 2];
85 uint32_t reserved1[(0x10 - 0x4) >> 2];
87 uint32_t reserved2[(0x18 - 0x14) >> 2];
90 uint32_t reserved3[(0x48 - 0x20) >> 2];
94 uint32_t reserved4[(0x10C - 0x54) >> 2];
[all …]
/freebsd/sys/arm/freescale/vybrid/
H A Dvf_anadig.c55 #define ANADIG_PLL3_CTRL 0x010 /* PLL3 Control */
56 #define ANADIG_PLL7_CTRL 0x020 /* PLL7 Control */
57 #define ANADIG_PLL2_CTRL 0x030 /* PLL2 Control */
58 #define ANADIG_PLL2_SS 0x040 /* PLL2 Spread Spectrum */
59 #define ANADIG_PLL2_NUM 0x050 /* PLL2 Numerator */
60 #define ANADIG_PLL2_DENOM 0x060 /* PLL2 Denominator */
61 #define ANADIG_PLL4_CTRL 0x070 /* PLL4 Control */
62 #define ANADIG_PLL4_NUM 0x080 /* PLL4 Numerator */
63 #define ANADIG_PLL4_DENOM 0x090 /* PLL4 Denominator */
64 #define ANADIG_PLL6_CTRL 0x0A0 /* PLL6 Control */
[all …]
/freebsd/sys/amd64/vmm/io/
H A Dvlapic_priv.h37 #define APIC_OFFSET_ID 0x20 /* Local APIC ID */
38 #define APIC_OFFSET_VER 0x30 /* Local APIC Version */
39 #define APIC_OFFSET_TPR 0x80 /* Task Priority Register */
40 #define APIC_OFFSET_APR 0x90 /* Arbitration Priority */
41 #define APIC_OFFSET_PPR 0xA0 /* Processor Priority Register */
42 #define APIC_OFFSET_EOI 0xB0 /* EOI Register */
43 #define APIC_OFFSET_RRR 0xC0 /* Remote read */
44 #define APIC_OFFSET_LDR 0xD0 /* Logical Destination */
45 #define APIC_OFFSET_DFR 0xE0 /* Destination Format Register */
46 #define APIC_OFFSET_SVR 0xF0 /* Spurious Vector Register */
[all …]
/freebsd/sys/dev/cxgbe/cudbg/
H A Dcudbg_entity.h42 #define NUM_PCIE_CONFIG_REGS 0x61
51 #define CUDBG_MAX_TCAM_TID 0x800
55 #define SN_REG_ADDR 0x183f
56 #define BN_REG_ADDR 0x1819
57 #define NA_REG_ADDR 0x185a
58 #define MN_REG_ADDR 0x1803
60 #define A_MPS_VF_RPLCT_MAP0 0x1111c
61 #define A_MPS_VF_RPLCT_MAP1 0x11120
62 #define A_MPS_VF_RPLCT_MAP2 0x11124
63 #define A_MPS_VF_RPLCT_MAP3 0x11128
[all …]
/freebsd/sys/dev/dwc/
H A Ddwc1000_reg.h37 #define MAC_CONFIGURATION 0x0
47 #define MAC_FRAME_FILTER 0x4
53 #define FRAME_FILTER_PR (1 << 0) /* All Incoming Frames */
54 #define GMAC_MAC_HTHIGH 0x08
55 #define GMAC_MAC_HTLOW 0x0c
56 #define GMII_ADDRESS 0x10
57 #define GMII_ADDRESS_PA_MASK 0x1f /* Phy device */
59 #define GMII_ADDRESS_GR_MASK 0x1f /* Phy register */
61 #define GMII_ADDRESS_CR_MASK 0xf
64 #define GMII_ADDRESS_GB (1 << 0) /* Busy */
[all …]
/freebsd/sys/dev/ffec/
H A Dif_ffecreg.h41 #define FEC_IER_REG 0x0004
42 #define FEC_IEM_REG 0x0008
61 #define FEC_RDAR_REG 0x0010
64 #define FEC_TDAR_REG 0x0014
67 #define FEC_ECR_REG 0x0024
76 #define FEC_ECR_RESET (1 << 0)
78 #define FEC_MMFR_REG 0x0040
80 #define FEC_MMFR_ST_VALUE (0x01 << FEC_MMFR_ST_SHIFT)
82 #define FEC_MMFR_OP_WRITE (0x01 << FEC_MMFR_OP_SHIFT)
83 #define FEC_MMFR_OP_READ (0x02 << FEC_MMFR_OP_SHIFT)
[all …]
/freebsd/contrib/expat/tests/
H A Dcommon.c112 = "<documentwitharidiculouslylongelementnametotease" /* 0x030 */
113 "aparticularcorneroftheallocationinXML_GetBuffers" /* 0x060 */
114 "othatwecanimprovethecoverageyetagain012345678901" /* 0x090 */
115 "123456789abcdef0123456789abcdef0123456789abcdef0" /* 0x0c0 */
116 "123456789abcdef0123456789abcdef0123456789abcdef0" /* 0x0f0 */
117 "123456789abcdef0123456789abcdef0123456789abcdef0" /* 0x120 */
118 "123456789abcdef0123456789abcdef0123456789abcdef0" /* 0x150 */
119 "123456789abcdef0123456789abcdef0123456789abcdef0" /* 0x180 */
120 "123456789abcdef0123456789abcdef0123456789abcdef0" /* 0x1b0 */
121 "123456789abcdef0123456789abcdef0123456789abcdef0" /* 0x1e
[all...]
/freebsd/sys/powerpc/pseries/
H A Dphyp-hvcall.h37 #define H_SUCCESS 0
172 #define H_SET_MODE_RSRC_CIABR 0x1 /* All versions */
173 #define H_SET_MODE_RSRC_DAWR0 0x2 /* All versions */
174 #define H_SET_MODE_RSRC_INTR_TRANS_MODE 0x3 /* All versions */
175 #define H_SET_MODE_RSRC_ILE 0x4 /* PAPR 2.8 / ISA 2.07 */
176 #define H_SET_MODE_RSRC_DAWR1 0x5 /* ISA 3.1 Future support */
179 #define PROC_TABLE_OP_MASK 0x18
180 #define PROC_TABLE_DEREG 0x10
181 #define PROC_TABLE_NEW 0x18
182 #define PROC_TABLE_TYPE_MASK 0x06
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dscorpion_reg_map.h77 volatile char pad__0[0x8]; /* 0x0 - 0x8 */
78 volatile u_int32_t MAC_DMA_CR; /* 0x8 - 0xc */
79 volatile char pad__1[0x8]; /* 0xc - 0x14 */
80 volatile u_int32_t MAC_DMA_CFG; /* 0x14 - 0x18 */
81 volatile u_int32_t MAC_DMA_RXBUFPTR_THRESH; /* 0x18 - 0x1c */
82 volatile u_int32_t MAC_DMA_TXDPPTR_THRESH; /* 0x1c - 0x20 */
83 volatile u_int32_t MAC_DMA_MIRT; /* 0x20 - 0x24 */
84 volatile u_int32_t MAC_DMA_GLOBAL_IER; /* 0x24 - 0x28 */
85 volatile u_int32_t MAC_DMA_TIMT; /* 0x28 - 0x2c */
86 volatile u_int32_t MAC_DMA_RIMT; /* 0x2c - 0x30 */
[all …]

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