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/linux/Documentation/devicetree/bindings/sound/
H A Drenesas,rz-ssi.yaml65 bits[0:9] - Specifies MID/RID value of a SSI channel as below
66 MID/RID value of SSI rx0 = 0x256
67 MID/RID value of SSI tx0 = 0x255
68 MID/RID value of SSI rx1 = 0x25a
69 MID/RID value of SSI tx1 = 0x259
70 MID/RID value of SSI rt2 = 0x25f
71 MID/RID value of SSI rx3 = 0x262
72 MID/RID value of SSI tx3 = 0x261
75 bit[11] - LVL = 0, Detects based on the edge
77 bit[15] - TM = 0, Single transfer mode
[all …]
/linux/lib/math/
H A Dint_log.c17 0x0000, 0x0171, 0x02e0, 0x044e, 0x05ba, 0x0725, 0x088e, 0x09f7,
18 0x0b5d, 0x0cc3, 0x0e27, 0x0f8a, 0x10eb, 0x124b, 0x13aa, 0x1508,
19 0x1664, 0x17bf, 0x1919, 0x1a71, 0x1bc8, 0x1d1e, 0x1e73, 0x1fc6,
20 0x2119, 0x226a, 0x23ba, 0x2508, 0x2656, 0x27a2, 0x28ed, 0x2a37,
21 0x2b80, 0x2cc8, 0x2e0f, 0x2f54, 0x3098, 0x31dc, 0x331e, 0x345f,
22 0x359f, 0x36de, 0x381b, 0x3958, 0x3a94, 0x3bce, 0x3d08, 0x3e41,
23 0x3f78, 0x40af, 0x41e4, 0x4319, 0x444c, 0x457f, 0x46b0, 0x47e1,
24 0x4910, 0x4a3f, 0x4b6c, 0x4c99, 0x4dc5, 0x4eef, 0x5019, 0x5142,
25 0x526a, 0x5391, 0x54b7, 0x55dc, 0x5700, 0x5824, 0x5946, 0x5a68,
26 0x5b89, 0x5ca8, 0x5dc7, 0x5ee5, 0x6003, 0x611f, 0x623a, 0x6355,
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g043.dtsi17 #clock-cells = <0>;
19 clock-frequency = <0>;
24 #clock-cells = <0>;
26 clock-frequency = <0>;
32 #clock-cells = <0>;
33 clock-frequency = <0>;
39 #clock-cells = <0>;
41 clock-frequency = <0>;
44 cluster0_opp: opp-table-0 {
80 reg = <0 0x10001200 0 0xb00>;
[all …]
H A Dr9a07g054.dtsi18 #clock-cells = <0>;
20 clock-frequency = <0>;
25 #clock-cells = <0>;
27 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
40 #clock-cells = <0>;
42 clock-frequency = <0>;
45 cluster0_opp: opp-table-0 {
74 #size-cells = <0>;
[all …]
H A Dr9a07g044.dtsi18 #clock-cells = <0>;
20 clock-frequency = <0>;
25 #clock-cells = <0>;
27 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
40 #clock-cells = <0>;
42 clock-frequency = <0>;
45 cluster0_opp: opp-table-0 {
74 #size-cells = <0>;
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h26 #define ixCLIPPER_DEBUG_REG00 0x0000
27 #define ixCLIPPER_DEBUG_REG01 0x0001
28 #define ixCLIPPER_DEBUG_REG02 0x0002
29 #define ixCLIPPER_DEBUG_REG03 0x0003
30 #define ixCLIPPER_DEBUG_REG04 0x0004
31 #define ixCLIPPER_DEBUG_REG05 0x0005
32 #define ixCLIPPER_DEBUG_REG06 0x0006
33 #define ixCLIPPER_DEBUG_REG07 0x0007
34 #define ixCLIPPER_DEBUG_REG08 0x0008
35 #define ixCLIPPER_DEBUG_REG09 0x0009
[all …]
H A Dgfx_7_2_d.h27 #define mmCB_BLEND_RED 0xa105
28 #define mmCB_BLEND_GREEN 0xa106
29 #define mmCB_BLEND_BLUE 0xa107
30 #define mmCB_BLEND_ALPHA 0xa108
31 #define mmCB_COLOR_CONTROL 0xa202
32 #define mmCB_BLEND0_CONTROL 0xa1e0
33 #define mmCB_BLEND1_CONTROL 0xa1e1
34 #define mmCB_BLEND2_CONTROL 0xa1e2
35 #define mmCB_BLEND3_CONTROL 0xa1e3
36 #define mmCB_BLEND4_CONTROL 0xa1e4
[all …]
H A Dgfx_7_0_d.h27 #define mmCB_BLEND_RED 0xa105
28 #define mmCB_BLEND_GREEN 0xa106
29 #define mmCB_BLEND_BLUE 0xa107
30 #define mmCB_BLEND_ALPHA 0xa108
31 #define mmCB_COLOR_CONTROL 0xa202
32 #define mmCB_BLEND0_CONTROL 0xa1e0
33 #define mmCB_BLEND1_CONTROL 0xa1e1
34 #define mmCB_BLEND2_CONTROL 0xa1e2
35 #define mmCB_BLEND3_CONTROL 0xa1e3
36 #define mmCB_BLEND4_CONTROL 0xa1e4
[all …]
H A Dgfx_8_0_d.h27 #define mmCB_BLEND_RED 0xa105
28 #define mmCB_BLEND_GREEN 0xa106
29 #define mmCB_BLEND_BLUE 0xa107
30 #define mmCB_BLEND_ALPHA 0xa108
31 #define mmCB_DCC_CONTROL 0xa109
32 #define mmCB_COLOR_CONTROL 0xa202
33 #define mmCB_BLEND0_CONTROL 0xa1e0
34 #define mmCB_BLEND1_CONTROL 0xa1e1
35 #define mmCB_BLEND2_CONTROL 0xa1e2
36 #define mmCB_BLEND3_CONTROL 0xa1e3
[all …]
H A Dgfx_8_1_d.h27 #define mmCB_BLEND_RED 0xa105
28 #define mmCB_BLEND_GREEN 0xa106
29 #define mmCB_BLEND_BLUE 0xa107
30 #define mmCB_BLEND_ALPHA 0xa108
31 #define mmCB_DCC_CONTROL 0xa109
32 #define mmCB_COLOR_CONTROL 0xa202
33 #define mmCB_BLEND0_CONTROL 0xa1e0
34 #define mmCB_BLEND1_CONTROL 0xa1e1
35 #define mmCB_BLEND2_CONTROL 0xa1e2
36 #define mmCB_BLEND3_CONTROL 0xa1e3
[all …]
/linux/drivers/media/i2c/
H A Dov2659.c31 #define REG_SOFTWARE_STANDBY 0x0100
32 #define REG_SOFTWARE_RESET 0x0103
33 #define REG_IO_CTRL00 0x3000
34 #define REG_IO_CTRL01 0x3001
35 #define REG_IO_CTRL02 0x3002
36 #define REG_OUTPUT_VALUE00 0x3008
37 #define REG_OUTPUT_VALUE01 0x3009
38 #define REG_OUTPUT_VALUE02 0x300d
39 #define REG_OUTPUT_SELECT00 0x300e
40 #define REG_OUTPUT_SELECT01 0x300f
[all …]
H A Dhi847.c25 #define HI847_REG_CHIP_ID 0x0716
26 #define HI847_CHIP_ID 0x0847
28 #define HI847_REG_MODE_SELECT 0x0B00
29 #define HI847_MODE_STANDBY 0x0000
30 #define HI847_MODE_STREAMING 0x0100
32 #define HI847_REG_MODE_TG 0x027E
33 #define HI847_REG_MODE_TG_ENABLE 0x0100
34 #define HI847_REG_MODE_TG_DISABLE 0x0000
37 #define HI847_REG_FLL 0x020E
38 #define HI847_FLL_30FPS 0x0B51
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsid.h29 #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003
30 #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002
31 #define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02010001
39 #define SI_MAX_BACKENDS_MASK 0xFF
40 #define SI_MAX_BACKENDS_PER_SE_MASK 0x0F
42 #define SI_MAX_SIMDS_MASK 0x0FFF
43 #define SI_MAX_SIMDS_PER_SE_MASK 0x00FF
45 #define SI_MAX_PIPES_MASK 0xFF
46 #define SI_MAX_PIPES_PER_SIMD_MASK 0x3F
47 #define SI_MAX_LDS_NUM 0xFFFF
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_offset.h27 // base address: 0x1300000
31 // base address: 0x1300000
35 // base address: 0x1300000
39 // base address: 0x1300000
43 // base address: 0x1300000
47 // base address: 0x1300020
51 // base address: 0x1300040
55 // base address: 0x1300060
59 // base address: 0x1300080
63 // base address: 0x13000a0
[all …]
H A Ddcn_3_0_2_offset.h27 // base address: 0x0
28 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
29 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
30 …VGA_MEM_READ_PAGE_ADDR 0x0001
31 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
32 …VGA_RENDER_CONTROL 0x0000
34 …VGA_SEQUENCER_RESET_CONTROL 0x0001
36 …VGA_MODE_CONTROL 0x0002
38 …VGA_SURFACE_PITCH_SELECT 0x0003
40 …VGA_MEMORY_BASE_ADDRESS 0x0004
[all …]
H A Ddcn_3_0_0_offset.h8 // base address: 0x0
9 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
10 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
11 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
12 …VGA_MEM_READ_PAGE_ADDR 0x0001
13 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
14 …VGA_RENDER_CONTROL 0x0000
16 …VGA_SEQUENCER_RESET_CONTROL 0x0001
18 …VGA_MODE_CONTROL 0x0002
20 …VGA_SURFACE_PITCH_SELECT 0x0003
[all …]
H A Ddcn_2_0_0_offset.h27 // base address: 0x0
28 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
29 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
30 …VGA_MEM_READ_PAGE_ADDR 0x0001
31 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
32 …VGA_RENDER_CONTROL 0x0000
34 …VGA_SEQUENCER_RESET_CONTROL 0x0001
36 …VGA_MODE_CONTROL 0x0002
38 …VGA_SURFACE_PITCH_SELECT 0x0003
40 …VGA_MEMORY_BASE_ADDRESS 0x0004
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_offset.h27 // base address: 0x48
28 …dispdec_VGA_MEM_WRITE_PAGE_ADDR 0x0012
29 …ne mmdispdec_VGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
33 // base address: 0x4c
34 …dispdec_VGA_MEM_READ_PAGE_ADDR 0x0014
35 …ne mmdispdec_VGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
39 // base address: 0x0
40 …DC_PERFMON0_PERFCOUNTER_CNTL 0x0020
42 …DC_PERFMON0_PERFCOUNTER_CNTL2 0x0021
44 …DC_PERFMON0_PERFCOUNTER_STATE 0x0022
[all …]