31 #define REG_SOFTWARE_STANDBY		0x0100
32 #define REG_SOFTWARE_RESET		0x0103
33 #define REG_IO_CTRL00			0x3000
34 #define REG_IO_CTRL01			0x3001
35 #define REG_IO_CTRL02			0x3002
36 #define REG_OUTPUT_VALUE00		0x3008
37 #define REG_OUTPUT_VALUE01		0x3009
38 #define REG_OUTPUT_VALUE02		0x300d
39 #define REG_OUTPUT_SELECT00		0x300e
40 #define REG_OUTPUT_SELECT01		0x300f
41 #define REG_OUTPUT_SELECT02		0x3010
42 #define REG_OUTPUT_DRIVE		0x3011
43 #define REG_INPUT_READOUT00		0x302d
44 #define REG_INPUT_READOUT01		0x302e
45 #define REG_INPUT_READOUT02		0x302f
47 #define REG_SC_PLL_CTRL0		0x3003
48 #define REG_SC_PLL_CTRL1		0x3004
49 #define REG_SC_PLL_CTRL2		0x3005
50 #define REG_SC_PLL_CTRL3		0x3006
51 #define REG_SC_CHIP_ID_H		0x300a
52 #define REG_SC_CHIP_ID_L		0x300b
53 #define REG_SC_PWC			0x3014
54 #define REG_SC_CLKRST0			0x301a
55 #define REG_SC_CLKRST1			0x301b
56 #define REG_SC_CLKRST2			0x301c
57 #define REG_SC_CLKRST3			0x301d
58 #define REG_SC_SUB_ID			0x302a
59 #define REG_SC_SCCB_ID			0x302b
61 #define REG_GROUP_ADDRESS_00		0x3200
62 #define REG_GROUP_ADDRESS_01		0x3201
63 #define REG_GROUP_ADDRESS_02		0x3202
64 #define REG_GROUP_ADDRESS_03		0x3203
65 #define REG_GROUP_ACCESS		0x3208
67 #define REG_AWB_R_GAIN_H		0x3400
68 #define REG_AWB_R_GAIN_L		0x3401
69 #define REG_AWB_G_GAIN_H		0x3402
70 #define REG_AWB_G_GAIN_L		0x3403
71 #define REG_AWB_B_GAIN_H		0x3404
72 #define REG_AWB_B_GAIN_L		0x3405
73 #define REG_AWB_MANUAL_CONTROL		0x3406
75 #define REG_TIMING_HS_H			0x3800
76 #define REG_TIMING_HS_L			0x3801
77 #define REG_TIMING_VS_H			0x3802
78 #define REG_TIMING_VS_L			0x3803
79 #define REG_TIMING_HW_H			0x3804
80 #define REG_TIMING_HW_L			0x3805
81 #define REG_TIMING_VH_H			0x3806
82 #define REG_TIMING_VH_L			0x3807
83 #define REG_TIMING_DVPHO_H		0x3808
84 #define REG_TIMING_DVPHO_L		0x3809
85 #define REG_TIMING_DVPVO_H		0x380a
86 #define REG_TIMING_DVPVO_L		0x380b
87 #define REG_TIMING_HTS_H		0x380c
88 #define REG_TIMING_HTS_L		0x380d
89 #define REG_TIMING_VTS_H		0x380e
90 #define REG_TIMING_VTS_L		0x380f
91 #define REG_TIMING_HOFFS_H		0x3810
92 #define REG_TIMING_HOFFS_L		0x3811
93 #define REG_TIMING_VOFFS_H		0x3812
94 #define REG_TIMING_VOFFS_L		0x3813
95 #define REG_TIMING_XINC			0x3814
96 #define REG_TIMING_YINC			0x3815
97 #define REG_TIMING_VERT_FORMAT		0x3820
98 #define REG_TIMING_HORIZ_FORMAT		0x3821
100 #define REG_FORMAT_CTRL00		0x4300
102 #define REG_VFIFO_READ_START_H		0x4608
103 #define REG_VFIFO_READ_START_L		0x4609
105 #define REG_DVP_CTRL02			0x4708
107 #define REG_ISP_CTRL00			0x5000
108 #define REG_ISP_CTRL01			0x5001
109 #define REG_ISP_CTRL02			0x5002
111 #define REG_LENC_RED_X0_H		0x500c
112 #define REG_LENC_RED_X0_L		0x500d
113 #define REG_LENC_RED_Y0_H		0x500e
114 #define REG_LENC_RED_Y0_L		0x500f
115 #define REG_LENC_RED_A1			0x5010
116 #define REG_LENC_RED_B1			0x5011
117 #define REG_LENC_RED_A2_B2		0x5012
118 #define REG_LENC_GREEN_X0_H		0x5013
119 #define REG_LENC_GREEN_X0_L		0x5014
120 #define REG_LENC_GREEN_Y0_H		0x5015
121 #define REG_LENC_GREEN_Y0_L		0x5016
122 #define REG_LENC_GREEN_A1		0x5017
123 #define REG_LENC_GREEN_B1		0x5018
124 #define REG_LENC_GREEN_A2_B2		0x5019
125 #define REG_LENC_BLUE_X0_H		0x501a
126 #define REG_LENC_BLUE_X0_L		0x501b
127 #define REG_LENC_BLUE_Y0_H		0x501c
128 #define REG_LENC_BLUE_Y0_L		0x501d
129 #define REG_LENC_BLUE_A1		0x501e
130 #define REG_LENC_BLUE_B1		0x501f
131 #define REG_LENC_BLUE_A2_B2		0x5020
133 #define REG_AWB_CTRL00			0x5035
134 #define REG_AWB_CTRL01			0x5036
135 #define REG_AWB_CTRL02			0x5037
136 #define REG_AWB_CTRL03			0x5038
137 #define REG_AWB_CTRL04			0x5039
138 #define REG_AWB_LOCAL_LIMIT		0x503a
139 #define REG_AWB_CTRL12			0x5049
140 #define REG_AWB_CTRL13			0x504a
141 #define REG_AWB_CTRL14			0x504b
143 #define REG_SHARPENMT_THRESH1		0x5064
144 #define REG_SHARPENMT_THRESH2		0x5065
145 #define REG_SHARPENMT_OFFSET1		0x5066
146 #define REG_SHARPENMT_OFFSET2		0x5067
147 #define REG_DENOISE_THRESH1		0x5068
148 #define REG_DENOISE_THRESH2		0x5069
149 #define REG_DENOISE_OFFSET1		0x506a
150 #define REG_DENOISE_OFFSET2		0x506b
151 #define REG_SHARPEN_THRESH1		0x506c
152 #define REG_SHARPEN_THRESH2		0x506d
153 #define REG_CIP_CTRL00			0x506e
154 #define REG_CIP_CTRL01			0x506f
156 #define REG_CMX_SIGN			0x5079
157 #define REG_CMX_MISC_CTRL		0x507a
159 #define REG_PRE_ISP_CTRL00		0x50a0
161 #define VERTICAL_COLOR_BAR_MASK		0x53
163 #define REG_NULL			0x0000	/* Array end token */
166 #define OV2659_ID			0x2656
219 	{ REG_IO_CTRL00, 0x03 },
220 	{ REG_IO_CTRL01, 0xff },
221 	{ REG_IO_CTRL02, 0xe0 },
222 	{ 0x3633, 0x3d },
223 	{ 0x3620, 0x02 },
224 	{ 0x3631, 0x11 },
225 	{ 0x3612, 0x04 },
226 	{ 0x3630, 0x20 },
227 	{ 0x4702, 0x02 },
228 	{ 0x370c, 0x34 },
229 	{ REG_TIMING_HS_H, 0x00 },
230 	{ REG_TIMING_HS_L, 0x00 },
231 	{ REG_TIMING_VS_H, 0x00 },
232 	{ REG_TIMING_VS_L, 0x00 },
233 	{ REG_TIMING_HW_H, 0x06 },
234 	{ REG_TIMING_HW_L, 0x5f },
235 	{ REG_TIMING_VH_H, 0x04 },
236 	{ REG_TIMING_VH_L, 0xb7 },
237 	{ REG_TIMING_DVPHO_H, 0x03 },
238 	{ REG_TIMING_DVPHO_L, 0x20 },
239 	{ REG_TIMING_DVPVO_H, 0x02 },
240 	{ REG_TIMING_DVPVO_L, 0x58 },
241 	{ REG_TIMING_HTS_H, 0x05 },
242 	{ REG_TIMING_HTS_L, 0x14 },
243 	{ REG_TIMING_VTS_H, 0x02 },
244 	{ REG_TIMING_VTS_L, 0x68 },
245 	{ REG_TIMING_HOFFS_L, 0x08 },
246 	{ REG_TIMING_VOFFS_L, 0x02 },
247 	{ REG_TIMING_XINC, 0x31 },
248 	{ REG_TIMING_YINC, 0x31 },
249 	{ 0x3a02, 0x02 },
250 	{ 0x3a03, 0x68 },
251 	{ 0x3a08, 0x00 },
252 	{ 0x3a09, 0x5c },
253 	{ 0x3a0a, 0x00 },
254 	{ 0x3a0b, 0x4d },
255 	{ 0x3a0d, 0x08 },
256 	{ 0x3a0e, 0x06 },
257 	{ 0x3a14, 0x02 },
258 	{ 0x3a15, 0x28 },
259 	{ REG_DVP_CTRL02, 0x01 },
260 	{ 0x3623, 0x00 },
261 	{ 0x3634, 0x76 },
262 	{ 0x3701, 0x44 },
263 	{ 0x3702, 0x18 },
264 	{ 0x3703, 0x24 },
265 	{ 0x3704, 0x24 },
266 	{ 0x3705, 0x0c },
267 	{ REG_TIMING_VERT_FORMAT, 0x81 },
268 	{ REG_TIMING_HORIZ_FORMAT, 0x01 },
269 	{ 0x370a, 0x52 },
270 	{ REG_VFIFO_READ_START_H, 0x00 },
271 	{ REG_VFIFO_READ_START_L, 0x80 },
272 	{ REG_FORMAT_CTRL00, 0x30 },
273 	{ 0x5086, 0x02 },
274 	{ REG_ISP_CTRL00, 0xfb },
275 	{ REG_ISP_CTRL01, 0x1f },
276 	{ REG_ISP_CTRL02, 0x00 },
277 	{ 0x5025, 0x0e },
278 	{ 0x5026, 0x18 },
279 	{ 0x5027, 0x34 },
280 	{ 0x5028, 0x4c },
281 	{ 0x5029, 0x62 },
282 	{ 0x502a, 0x74 },
283 	{ 0x502b, 0x85 },
284 	{ 0x502c, 0x92 },
285 	{ 0x502d, 0x9e },
286 	{ 0x502e, 0xb2 },
287 	{ 0x502f, 0xc0 },
288 	{ 0x5030, 0xcc },
289 	{ 0x5031, 0xe0 },
290 	{ 0x5032, 0xee },
291 	{ 0x5033, 0xf6 },
292 	{ 0x5034, 0x11 },
293 	{ 0x5070, 0x1c },
294 	{ 0x5071, 0x5b },
295 	{ 0x5072, 0x05 },
296 	{ 0x5073, 0x20 },
297 	{ 0x5074, 0x94 },
298 	{ 0x5075, 0xb4 },
299 	{ 0x5076, 0xb4 },
300 	{ 0x5077, 0xaf },
301 	{ 0x5078, 0x05 },
302 	{ REG_CMX_SIGN, 0x98 },
303 	{ REG_CMX_MISC_CTRL, 0x21 },
304 	{ REG_AWB_CTRL00, 0x6a },
305 	{ REG_AWB_CTRL01, 0x11 },
306 	{ REG_AWB_CTRL02, 0x92 },
307 	{ REG_AWB_CTRL03, 0x21 },
308 	{ REG_AWB_CTRL04, 0xe1 },
309 	{ REG_AWB_LOCAL_LIMIT, 0x01 },
310 	{ 0x503c, 0x05 },
311 	{ 0x503d, 0x08 },
312 	{ 0x503e, 0x08 },
313 	{ 0x503f, 0x64 },
314 	{ 0x5040, 0x58 },
315 	{ 0x5041, 0x2a },
316 	{ 0x5042, 0xc5 },
317 	{ 0x5043, 0x2e },
318 	{ 0x5044, 0x3a },
319 	{ 0x5045, 0x3c },
320 	{ 0x5046, 0x44 },
321 	{ 0x5047, 0xf8 },
322 	{ 0x5048, 0x08 },
323 	{ REG_AWB_CTRL12, 0x70 },
324 	{ REG_AWB_CTRL13, 0xf0 },
325 	{ REG_AWB_CTRL14, 0xf0 },
326 	{ REG_LENC_RED_X0_H, 0x03 },
327 	{ REG_LENC_RED_X0_L, 0x20 },
328 	{ REG_LENC_RED_Y0_H, 0x02 },
329 	{ REG_LENC_RED_Y0_L, 0x5c },
330 	{ REG_LENC_RED_A1, 0x48 },
331 	{ REG_LENC_RED_B1, 0x00 },
332 	{ REG_LENC_RED_A2_B2, 0x66 },
333 	{ REG_LENC_GREEN_X0_H, 0x03 },
334 	{ REG_LENC_GREEN_X0_L, 0x30 },
335 	{ REG_LENC_GREEN_Y0_H, 0x02 },
336 	{ REG_LENC_GREEN_Y0_L, 0x7c },
337 	{ REG_LENC_GREEN_A1, 0x40 },
338 	{ REG_LENC_GREEN_B1, 0x00 },
339 	{ REG_LENC_GREEN_A2_B2, 0x66 },
340 	{ REG_LENC_BLUE_X0_H, 0x03 },
341 	{ REG_LENC_BLUE_X0_L, 0x10 },
342 	{ REG_LENC_BLUE_Y0_H, 0x02 },
343 	{ REG_LENC_BLUE_Y0_L, 0x7c },
344 	{ REG_LENC_BLUE_A1, 0x3a },
345 	{ REG_LENC_BLUE_B1, 0x00 },
346 	{ REG_LENC_BLUE_A2_B2, 0x66 },
347 	{ REG_CIP_CTRL00, 0x44 },
348 	{ REG_SHARPENMT_THRESH1, 0x08 },
349 	{ REG_SHARPENMT_THRESH2, 0x10 },
350 	{ REG_SHARPENMT_OFFSET1, 0x12 },
351 	{ REG_SHARPENMT_OFFSET2, 0x02 },
352 	{ REG_SHARPEN_THRESH1, 0x08 },
353 	{ REG_SHARPEN_THRESH2, 0x10 },
354 	{ REG_CIP_CTRL01, 0xa6 },
355 	{ REG_DENOISE_THRESH1, 0x08 },
356 	{ REG_DENOISE_THRESH2, 0x10 },
357 	{ REG_DENOISE_OFFSET1, 0x04 },
358 	{ REG_DENOISE_OFFSET2, 0x12 },
359 	{ 0x507e, 0x40 },
360 	{ 0x507f, 0x20 },
361 	{ 0x507b, 0x02 },
362 	{ REG_CMX_MISC_CTRL, 0x01 },
363 	{ 0x5084, 0x0c },
364 	{ 0x5085, 0x3e },
365 	{ 0x5005, 0x80 },
366 	{ 0x3a0f, 0x30 },
367 	{ 0x3a10, 0x28 },
368 	{ 0x3a1b, 0x32 },
369 	{ 0x3a1e, 0x26 },
370 	{ 0x3a11, 0x60 },
371 	{ 0x3a1f, 0x14 },
372 	{ 0x5060, 0x69 },
373 	{ 0x5061, 0x7d },
374 	{ 0x5062, 0x7d },
375 	{ 0x5063, 0x69 },
376 	{ REG_NULL, 0x00 },
381 	{ REG_TIMING_HS_H, 0x00 },
382 	{ REG_TIMING_HS_L, 0xa0 },
383 	{ REG_TIMING_VS_H, 0x00 },
384 	{ REG_TIMING_VS_L, 0xf0 },
385 	{ REG_TIMING_HW_H, 0x05 },
386 	{ REG_TIMING_HW_L, 0xbf },
387 	{ REG_TIMING_VH_H, 0x03 },
388 	{ REG_TIMING_VH_L, 0xcb },
389 	{ REG_TIMING_DVPHO_H, 0x05 },
390 	{ REG_TIMING_DVPHO_L, 0x00 },
391 	{ REG_TIMING_DVPVO_H, 0x02 },
392 	{ REG_TIMING_DVPVO_L, 0xd0 },
393 	{ REG_TIMING_HTS_H, 0x06 },
394 	{ REG_TIMING_HTS_L, 0x4c },
395 	{ REG_TIMING_VTS_H, 0x02 },
396 	{ REG_TIMING_VTS_L, 0xe8 },
397 	{ REG_TIMING_HOFFS_L, 0x10 },
398 	{ REG_TIMING_VOFFS_L, 0x06 },
399 	{ REG_TIMING_XINC, 0x11 },
400 	{ REG_TIMING_YINC, 0x11 },
401 	{ REG_TIMING_VERT_FORMAT, 0x80 },
402 	{ REG_TIMING_HORIZ_FORMAT, 0x00 },
403 	{ 0x370a, 0x12 },
404 	{ 0x3a03, 0xe8 },
405 	{ 0x3a09, 0x6f },
406 	{ 0x3a0b, 0x5d },
407 	{ 0x3a15, 0x9a },
408 	{ REG_VFIFO_READ_START_H, 0x00 },
409 	{ REG_VFIFO_READ_START_L, 0x80 },
410 	{ REG_ISP_CTRL02, 0x00 },
411 	{ REG_NULL, 0x00 },
416 	{ REG_TIMING_HS_H, 0x00 },
417 	{ REG_TIMING_HS_L, 0x00 },
418 	{ REG_TIMING_VS_H, 0x00 },
419 	{ REG_TIMING_VS_L, 0x00 },
420 	{ REG_TIMING_HW_H, 0x06 },
421 	{ REG_TIMING_HW_L, 0x5f },
422 	{ REG_TIMING_VH_H, 0x04 },
423 	{ REG_TIMING_VH_L, 0xbb },
424 	{ REG_TIMING_DVPHO_H, 0x06 },
425 	{ REG_TIMING_DVPHO_L, 0x40 },
426 	{ REG_TIMING_DVPVO_H, 0x04 },
427 	{ REG_TIMING_DVPVO_L, 0xb0 },
428 	{ REG_TIMING_HTS_H, 0x07 },
429 	{ REG_TIMING_HTS_L, 0x9f },
430 	{ REG_TIMING_VTS_H, 0x04 },
431 	{ REG_TIMING_VTS_L, 0xd0 },
432 	{ REG_TIMING_HOFFS_L, 0x10 },
433 	{ REG_TIMING_VOFFS_L, 0x06 },
434 	{ REG_TIMING_XINC, 0x11 },
435 	{ REG_TIMING_YINC, 0x11 },
436 	{ 0x3a02, 0x04 },
437 	{ 0x3a03, 0xd0 },
438 	{ 0x3a08, 0x00 },
439 	{ 0x3a09, 0xb8 },
440 	{ 0x3a0a, 0x00 },
441 	{ 0x3a0b, 0x9a },
442 	{ 0x3a0d, 0x08 },
443 	{ 0x3a0e, 0x06 },
444 	{ 0x3a14, 0x04 },
445 	{ 0x3a15, 0x50 },
446 	{ 0x3623, 0x00 },
447 	{ 0x3634, 0x44 },
448 	{ 0x3701, 0x44 },
449 	{ 0x3702, 0x30 },
450 	{ 0x3703, 0x48 },
451 	{ 0x3704, 0x48 },
452 	{ 0x3705, 0x18 },
453 	{ REG_TIMING_VERT_FORMAT, 0x80 },
454 	{ REG_TIMING_HORIZ_FORMAT, 0x00 },
455 	{ 0x370a, 0x12 },
456 	{ REG_VFIFO_READ_START_H, 0x00 },
457 	{ REG_VFIFO_READ_START_L, 0x80 },
458 	{ REG_ISP_CTRL02, 0x00 },
459 	{ REG_NULL, 0x00 },
464 	{ REG_TIMING_HS_H, 0x00 },
465 	{ REG_TIMING_HS_L, 0x00 },
466 	{ REG_TIMING_VS_H, 0x00 },
467 	{ REG_TIMING_VS_L, 0x00 },
468 	{ REG_TIMING_HW_H, 0x06 },
469 	{ REG_TIMING_HW_L, 0x5f },
470 	{ REG_TIMING_VH_H, 0x04 },
471 	{ REG_TIMING_VH_L, 0xb7 },
472 	{ REG_TIMING_DVPHO_H, 0x05 },
473 	{ REG_TIMING_DVPHO_L, 0x00 },
474 	{ REG_TIMING_DVPVO_H, 0x04 },
475 	{ REG_TIMING_DVPVO_L, 0x00 },
476 	{ REG_TIMING_HTS_H, 0x07 },
477 	{ REG_TIMING_HTS_L, 0x9c },
478 	{ REG_TIMING_VTS_H, 0x04 },
479 	{ REG_TIMING_VTS_L, 0xd0 },
480 	{ REG_TIMING_HOFFS_L, 0x10 },
481 	{ REG_TIMING_VOFFS_L, 0x06 },
482 	{ REG_TIMING_XINC, 0x11 },
483 	{ REG_TIMING_YINC, 0x11 },
484 	{ 0x3a02, 0x02 },
485 	{ 0x3a03, 0x68 },
486 	{ 0x3a08, 0x00 },
487 	{ 0x3a09, 0x5c },
488 	{ 0x3a0a, 0x00 },
489 	{ 0x3a0b, 0x4d },
490 	{ 0x3a0d, 0x08 },
491 	{ 0x3a0e, 0x06 },
492 	{ 0x3a14, 0x02 },
493 	{ 0x3a15, 0x28 },
494 	{ 0x3623, 0x00 },
495 	{ 0x3634, 0x76 },
496 	{ 0x3701, 0x44 },
497 	{ 0x3702, 0x18 },
498 	{ 0x3703, 0x24 },
499 	{ 0x3704, 0x24 },
500 	{ 0x3705, 0x0c },
501 	{ REG_TIMING_VERT_FORMAT, 0x80 },
502 	{ REG_TIMING_HORIZ_FORMAT, 0x00 },
503 	{ 0x370a, 0x52 },
504 	{ REG_VFIFO_READ_START_H, 0x00 },
505 	{ REG_VFIFO_READ_START_L, 0x80 },
506 	{ REG_ISP_CTRL02, 0x00 },
507 	{ REG_NULL, 0x00 },
512 	{ REG_TIMING_HS_H, 0x00 },
513 	{ REG_TIMING_HS_L, 0x00 },
514 	{ REG_TIMING_VS_H, 0x00 },
515 	{ REG_TIMING_VS_L, 0x00 },
516 	{ REG_TIMING_HW_H, 0x06 },
517 	{ REG_TIMING_HW_L, 0x5f },
518 	{ REG_TIMING_VH_H, 0x04 },
519 	{ REG_TIMING_VH_L, 0xb7 },
520 	{ REG_TIMING_DVPHO_H, 0x04 },
521 	{ REG_TIMING_DVPHO_L, 0x00 },
522 	{ REG_TIMING_DVPVO_H, 0x03 },
523 	{ REG_TIMING_DVPVO_L, 0x00 },
524 	{ REG_TIMING_HTS_H, 0x07 },
525 	{ REG_TIMING_HTS_L, 0x9c },
526 	{ REG_TIMING_VTS_H, 0x04 },
527 	{ REG_TIMING_VTS_L, 0xd0 },
528 	{ REG_TIMING_HOFFS_L, 0x10 },
529 	{ REG_TIMING_VOFFS_L, 0x06 },
530 	{ REG_TIMING_XINC, 0x11 },
531 	{ REG_TIMING_YINC, 0x11 },
532 	{ 0x3a02, 0x02 },
533 	{ 0x3a03, 0x68 },
534 	{ 0x3a08, 0x00 },
535 	{ 0x3a09, 0x5c },
536 	{ 0x3a0a, 0x00 },
537 	{ 0x3a0b, 0x4d },
538 	{ 0x3a0d, 0x08 },
539 	{ 0x3a0e, 0x06 },
540 	{ 0x3a14, 0x02 },
541 	{ 0x3a15, 0x28 },
542 	{ 0x3623, 0x00 },
543 	{ 0x3634, 0x76 },
544 	{ 0x3701, 0x44 },
545 	{ 0x3702, 0x18 },
546 	{ 0x3703, 0x24 },
547 	{ 0x3704, 0x24 },
548 	{ 0x3705, 0x0c },
549 	{ REG_TIMING_VERT_FORMAT, 0x80 },
550 	{ REG_TIMING_HORIZ_FORMAT, 0x00 },
551 	{ 0x370a, 0x52 },
552 	{ REG_VFIFO_READ_START_H, 0x00 },
553 	{ REG_VFIFO_READ_START_L, 0x80 },
554 	{ REG_ISP_CTRL02, 0x00 },
555 	{ REG_NULL, 0x00 },
560 	{ REG_TIMING_HS_H, 0x00 },
561 	{ REG_TIMING_HS_L, 0x00 },
562 	{ REG_TIMING_VS_H, 0x00 },
563 	{ REG_TIMING_VS_L, 0x00 },
564 	{ REG_TIMING_HW_H, 0x06 },
565 	{ REG_TIMING_HW_L, 0x5f },
566 	{ REG_TIMING_VH_H, 0x04 },
567 	{ REG_TIMING_VH_L, 0xb7 },
568 	{ REG_TIMING_DVPHO_H, 0x03 },
569 	{ REG_TIMING_DVPHO_L, 0x20 },
570 	{ REG_TIMING_DVPVO_H, 0x02 },
571 	{ REG_TIMING_DVPVO_L, 0x58 },
572 	{ REG_TIMING_HTS_H, 0x05 },
573 	{ REG_TIMING_HTS_L, 0x14 },
574 	{ REG_TIMING_VTS_H, 0x02 },
575 	{ REG_TIMING_VTS_L, 0x68 },
576 	{ REG_TIMING_HOFFS_L, 0x08 },
577 	{ REG_TIMING_VOFFS_L, 0x02 },
578 	{ REG_TIMING_XINC, 0x31 },
579 	{ REG_TIMING_YINC, 0x31 },
580 	{ 0x3a02, 0x02 },
581 	{ 0x3a03, 0x68 },
582 	{ 0x3a08, 0x00 },
583 	{ 0x3a09, 0x5c },
584 	{ 0x3a0a, 0x00 },
585 	{ 0x3a0b, 0x4d },
586 	{ 0x3a0d, 0x08 },
587 	{ 0x3a0e, 0x06 },
588 	{ 0x3a14, 0x02 },
589 	{ 0x3a15, 0x28 },
590 	{ 0x3623, 0x00 },
591 	{ 0x3634, 0x76 },
592 	{ 0x3701, 0x44 },
593 	{ 0x3702, 0x18 },
594 	{ 0x3703, 0x24 },
595 	{ 0x3704, 0x24 },
596 	{ 0x3705, 0x0c },
597 	{ REG_TIMING_VERT_FORMAT, 0x81 },
598 	{ REG_TIMING_HORIZ_FORMAT, 0x01 },
599 	{ 0x370a, 0x52 },
600 	{ REG_VFIFO_READ_START_H, 0x00 },
601 	{ REG_VFIFO_READ_START_L, 0x80 },
602 	{ REG_ISP_CTRL02, 0x00 },
603 	{ REG_NULL, 0x00 },
608 	{ REG_TIMING_HS_H, 0x00 },
609 	{ REG_TIMING_HS_L, 0x00 },
610 	{ REG_TIMING_VS_H, 0x00 },
611 	{ REG_TIMING_VS_L, 0x00 },
612 	{ REG_TIMING_HW_H, 0x06 },
613 	{ REG_TIMING_HW_L, 0x5f },
614 	{ REG_TIMING_VH_H, 0x04 },
615 	{ REG_TIMING_VH_L, 0xb7 },
616 	{ REG_TIMING_DVPHO_H, 0x02 },
617 	{ REG_TIMING_DVPHO_L, 0x80 },
618 	{ REG_TIMING_DVPVO_H, 0x01 },
619 	{ REG_TIMING_DVPVO_L, 0xe0 },
620 	{ REG_TIMING_HTS_H, 0x05 },
621 	{ REG_TIMING_HTS_L, 0x14 },
622 	{ REG_TIMING_VTS_H, 0x02 },
623 	{ REG_TIMING_VTS_L, 0x68 },
624 	{ REG_TIMING_HOFFS_L, 0x08 },
625 	{ REG_TIMING_VOFFS_L, 0x02 },
626 	{ REG_TIMING_XINC, 0x31 },
627 	{ REG_TIMING_YINC, 0x31 },
628 	{ 0x3a02, 0x02 },
629 	{ 0x3a03, 0x68 },
630 	{ 0x3a08, 0x00 },
631 	{ 0x3a09, 0x5c },
632 	{ 0x3a0a, 0x00 },
633 	{ 0x3a0b, 0x4d },
634 	{ 0x3a0d, 0x08 },
635 	{ 0x3a0e, 0x06 },
636 	{ 0x3a14, 0x02 },
637 	{ 0x3a15, 0x28 },
638 	{ 0x3623, 0x00 },
639 	{ 0x3634, 0x76 },
640 	{ 0x3701, 0x44 },
641 	{ 0x3702, 0x18 },
642 	{ 0x3703, 0x24 },
643 	{ 0x3704, 0x24 },
644 	{ 0x3705, 0x0c },
645 	{ REG_TIMING_VERT_FORMAT, 0x81 },
646 	{ REG_TIMING_HORIZ_FORMAT, 0x01 },
647 	{ 0x370a, 0x52 },
648 	{ REG_VFIFO_READ_START_H, 0x00 },
649 	{ REG_VFIFO_READ_START_L, 0xa0 },
650 	{ REG_ISP_CTRL02, 0x10 },
651 	{ REG_NULL, 0x00 },
656 	{ REG_TIMING_HS_H, 0x00 },
657 	{ REG_TIMING_HS_L, 0x00 },
658 	{ REG_TIMING_VS_H, 0x00 },
659 	{ REG_TIMING_VS_L, 0x00 },
660 	{ REG_TIMING_HW_H, 0x06 },
661 	{ REG_TIMING_HW_L, 0x5f },
662 	{ REG_TIMING_VH_H, 0x04 },
663 	{ REG_TIMING_VH_L, 0xb7 },
664 	{ REG_TIMING_DVPHO_H, 0x01 },
665 	{ REG_TIMING_DVPHO_L, 0x40 },
666 	{ REG_TIMING_DVPVO_H, 0x00 },
667 	{ REG_TIMING_DVPVO_L, 0xf0 },
668 	{ REG_TIMING_HTS_H, 0x05 },
669 	{ REG_TIMING_HTS_L, 0x14 },
670 	{ REG_TIMING_VTS_H, 0x02 },
671 	{ REG_TIMING_VTS_L, 0x68 },
672 	{ REG_TIMING_HOFFS_L, 0x08 },
673 	{ REG_TIMING_VOFFS_L, 0x02 },
674 	{ REG_TIMING_XINC, 0x31 },
675 	{ REG_TIMING_YINC, 0x31 },
676 	{ 0x3a02, 0x02 },
677 	{ 0x3a03, 0x68 },
678 	{ 0x3a08, 0x00 },
679 	{ 0x3a09, 0x5c },
680 	{ 0x3a0a, 0x00 },
681 	{ 0x3a0b, 0x4d },
682 	{ 0x3a0d, 0x08 },
683 	{ 0x3a0e, 0x06 },
684 	{ 0x3a14, 0x02 },
685 	{ 0x3a15, 0x28 },
686 	{ 0x3623, 0x00 },
687 	{ 0x3634, 0x76 },
688 	{ 0x3701, 0x44 },
689 	{ 0x3702, 0x18 },
690 	{ 0x3703, 0x24 },
691 	{ 0x3704, 0x24 },
692 	{ 0x3705, 0x0c },
693 	{ REG_TIMING_VERT_FORMAT, 0x81 },
694 	{ REG_TIMING_HORIZ_FORMAT, 0x01 },
695 	{ 0x370a, 0x52 },
696 	{ REG_VFIFO_READ_START_H, 0x00 },
697 	{ REG_VFIFO_READ_START_L, 0xa0 },
698 	{ REG_ISP_CTRL02, 0x10 },
699 	{ REG_NULL, 0x00 },
703 	{ 1, 0x00 },
704 	{ 2, 0x02 },
705 	{ 3, 0x03 },
706 	{ 4, 0x06 },
707 	{ 6, 0x0d },
708 	{ 8, 0x0e },
709 	{ 12, 0x0f },
710 	{ 16, 0x12 },
711 	{ 24, 0x13 },
712 	{ 32, 0x16 },
713 	{ 48, 0x1b },
714 	{ 64, 0x1e },
715 	{ 96, 0x1f },
716 	{ 0, 0x00 },
720 	{ 2, 0x10 },
721 	{ 4, 0x20 },
722 	{ 6, 0x30 },
723 	{ 8, 0x40 },
724 	{ 10, 0x50 },
725 	{ 12, 0x60 },
726 	{ 14, 0x70 },
727 	{ 16, 0x80 },
728 	{ 18, 0x90 },
729 	{ 20, 0xa0 },
730 	{ 22, 0xb0 },
731 	{ 24, 0xc0 },
732 	{ 26, 0xd0 },
733 	{ 28, 0xe0 },
734 	{ 30, 0xf0 },
735 	{ 0, 0x00 },
779 	{ REG_FORMAT_CTRL00, 0x30 },
780 	{ REG_NULL, 0x0 },
785 	{ REG_FORMAT_CTRL00, 0x32 },
786 	{ REG_NULL, 0x0 },
791 	{ REG_FORMAT_CTRL00, 0x00 },
792 	{ REG_NULL, 0x0 },
797 	{ REG_FORMAT_CTRL00, 0x60 },
798 	{ REG_NULL, 0x0 },
829 	buf[0] = reg >> 8;  in ov2659_write()
830 	buf[1] = reg & 0xFF;  in ov2659_write()
839 	if (ret >= 0)  in ov2659_write()
840 		return 0;  in ov2659_write()
843 		"ov2659 write reg(0x%x val:0x%x) failed !\n", reg, val);  in ov2659_write()
855 	buf[0] = reg >> 8;  in ov2659_read()
856 	buf[1] = reg & 0xFF;  in ov2659_read()
858 	msg[0].addr = client->addr;  in ov2659_read()
859 	msg[0].flags = client->flags;  in ov2659_read()
860 	msg[0].buf = buf;  in ov2659_read()
861 	msg[0].len = sizeof(buf);  in ov2659_read()
869 	if (ret >= 0) {  in ov2659_read()
870 		*val = buf[0];  in ov2659_read()
871 		return 0;  in ov2659_read()
875 		"ov2659 read reg(0x%x val:0x%x) failed !\n", reg, *val);  in ov2659_read()
883 	int i, ret = 0;  in ov2659_write_array()
885 	for (i = 0; ret == 0 && regs[i].addr; i++)  in ov2659_write_array()
894 	u8 ctrl1_reg = 0, ctrl2_reg = 0, ctrl3_reg = 0;  in ov2659_pll_calc_params()
902 	for (i = 0; ctrl1[i].div != 0; i++) {  in ov2659_pll_calc_params()
904 		for (j = 0; ctrl3[j].div != 0; j++) {  in ov2659_pll_calc_params()
940 		{REG_NULL, 0x00},  in ov2659_set_pixel_clock()
953 	format->code = ov2659_formats[0].code;  in ov2659_get_default_format()
995 	return 0;  in ov2659_enum_mbus_code()
1021 	return 0;  in ov2659_enum_frame_sizes()
1036 		mf = v4l2_subdev_state_get_format(sd_state, 0);  in ov2659_get_fmt()
1040 		return 0;  in ov2659_get_fmt()
1051 	return 0;  in ov2659_get_fmt()
1057 	const struct ov2659_framesize *fsize = &ov2659_framesizes[0];  in __ov2659_try_frame_size()
1065 		if ((err < min_err) && (fsize->regs[0].addr)) {  in __ov2659_try_frame_size()
1091 	int ret = 0;  in ov2659_set_fmt()
1097 	while (--index >= 0)  in ov2659_set_fmt()
1101 	if (index < 0) {  in ov2659_set_fmt()
1102 		index = 0;  in ov2659_set_fmt()
1133 		if (ret < 0)  in ov2659_set_fmt()
1165 	int ret = 0;  in ov2659_s_stream()
1178 		ov2659_set_streaming(ov2659, 0);  in ov2659_s_stream()
1185 	if (ret < 0)  in ov2659_s_stream()
1188 	ret = ov2659_init(sd, 0);  in ov2659_s_stream()
1212 	if (ret < 0)  in ov2659_set_test_pattern()
1216 	case 0:  in ov2659_set_test_pattern()
1236 		return 0;  in ov2659_s_ctrl()
1244 	return 0;  in ov2659_s_ctrl()
1268 	return 0;  in ov2659_power_off()
1287 	gpiod_set_value(ov2659->pwdn_gpio, 0);  in ov2659_power_on()
1292 		gpiod_set_value(ov2659->resetb_gpio, 0);  in ov2659_power_on()
1296 	return 0;  in ov2659_power_on()
1307 				v4l2_subdev_state_get_format(fh->state, 0);  in ov2659_open()
1313 	return 0;  in ov2659_open()
1346 	u8 pid = 0;  in ov2659_detect()
1347 	u8 ver = 0;  in ov2659_detect()
1352 	ret = ov2659_write(client, REG_SOFTWARE_RESET, 0x01);  in ov2659_detect()
1353 	if (ret != 0) {  in ov2659_detect()
1384 	struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 };  in ov2659_get_pdata()
1391 	endpoint = of_graph_get_endpoint_by_regs(client->dev.of_node, 0, -1);  in ov2659_get_pdata()
1413 	pdata->link_frequency = bus_cfg.link_frequencies[0];  in ov2659_get_pdata()
1471 				     0, 0, ov2659_test_pattern_menu);  in ov2659_probe()
1491 	if (ret < 0) {  in ov2659_probe()
1500 	ov2659->format_ctrl_regs = ov2659_formats[0].format_ctrl_regs;  in ov2659_probe()
1503 	if (ret < 0)  in ov2659_probe()
1507 	if (ret < 0)  in ov2659_probe()
1523 	return 0;  in ov2659_probe()