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/linux/arch/powerpc/boot/dts/fsl/
H A Dpq3-etsec1-2.dtsi2 * PQ3 eTSEC device tree stub [ @ offsets 0x26000 ]
42 reg = <0x26000 0x1000>;
43 ranges = <0x0 0x26000 0x1000>;
46 interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
51 #size-cells = <0>;
53 reg = <0x26520 0x20>;
H A Dpq3-etsec2-2.dtsi2 * PQ3 eTSEC2 device tree stub [ @ offsets 0x26000/0xb2000 ]
37 #size-cells = <0>;
39 reg = <0x26000 0x1000 0xb1030 0x4>;
48 fsl,num_rx_queues = <0x8>;
49 fsl,num_tx_queues = <0x8>;
57 reg = <0xb2000 0x1000>;
58 interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
/linux/arch/powerpc/boot/dts/
H A Dsocrates.dts27 #size-cells = <0>;
29 PowerPC,8544@0 {
31 reg = <0>;
34 d-cache-size = <0x8000>; // L1, 32K
35 i-cache-size = <0x8000>; // L1, 32K
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
45 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
53 ranges = <0x00000000 0xe0000000 0x00100000>;
[all …]
H A Dtqm8540.dts29 #size-cells = <0>;
31 PowerPC,8540@0 {
33 reg = <0>;
38 timebase-frequency = <0>;
39 bus-frequency = <0>;
40 clock-frequency = <0>;
47 reg = <0x00000000 0x10000000>;
54 ranges = <0x0 0xe0000000 0x100000>;
55 bus-frequency = <0>;
58 ecm-law@0 {
[all …]
H A Dxpedite5200.dts30 #size-cells = <0>;
32 PowerPC,8548@0 {
34 reg = <0>;
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
45 reg = <0x0 0x0>; // Filled in by U-Boot
52 ranges = <0x0 0xef000000 0x100000>;
53 bus-frequency = <0>;
56 ecm-law@0 {
58 reg = <0x0 0x1000>;
[all …]
H A Dtqm8548.dts31 #size-cells = <0>;
33 PowerPC,8548@0 {
35 reg = <0>;
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
46 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
53 ranges = <0x0 0xe0000000 0x100000>;
54 bus-frequency = <0>;
57 ecm-law@0 {
59 reg = <0x0 0x1000>;
[all …]
H A Dtqm8548-bigflash.dts31 #size-cells = <0>;
33 PowerPC,8548@0 {
35 reg = <0>;
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
46 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
53 ranges = <0x0 0xa0000000 0x100000>;
54 bus-frequency = <0>;
57 ecm-law@0 {
59 reg = <0x0 0x1000>;
[all …]
H A Dxpedite5200_xmon.dts18 boot-bank = <0x0>;
34 #size-cells = <0>;
36 PowerPC,8548@0 {
38 reg = <0>;
41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
49 reg = <0x0 0x0>; // Filled in by boot loader
56 ranges = <0x0 0xef000000 0x100000>;
57 bus-frequency = <0>;
60 ecm-law@0 {
[all …]
H A Dxcalibur1501.dts28 #size-cells = <0>;
30 PowerPC,8572@0 {
32 reg = <0x0>;
35 d-cache-size = <0x8000>; // L1, 32K
36 i-cache-size = <0x8000>; // L1, 32K
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
45 reg = <0x1>;
48 d-cache-size = <0x8000>; // L1, 32K
[all …]
/linux/Documentation/devicetree/bindings/bus/
H A Dqcom,ssc-block-bus.yaml125 reg = <0x10ac008 0x4>, <0x10ac010 0x4>;
142 qcom,halt-regs = <&tcsr_mutex_regs 0x26000>;
/linux/arch/arm/mach-imx/
H A Dmx2x.h16 #define MX2x_AIPI_BASE_ADDR 0x10000000
18 #define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000)
19 #define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000)
20 #define MX2x_GPT1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x03000)
21 #define MX2x_GPT2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x04000)
22 #define MX2x_GPT3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x05000)
23 #define MX2x_PWM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x06000)
24 #define MX2x_RTC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x07000)
25 #define MX2x_KPP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x08000)
26 #define MX2x_OWIRE_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x09000)
[all …]
/linux/drivers/gpu/drm/msm/adreno/
H A Da6xx_gpu_state.h16 0x8000, 0x8006, 0x8010, 0x8092, 0x8094, 0x809d, 0x80a0, 0x80a6,
17 0x80af, 0x80f1, 0x8100, 0x8107, 0x8109, 0x8109, 0x8110, 0x8110,
18 0x8400, 0x840b,
22 0x8800, 0x8806, 0x8809, 0x8811, 0x8818, 0x881e, 0x8820, 0x8865,
23 0x8870, 0x8879, 0x8880, 0x8889, 0x8890, 0x8891, 0x8898, 0x8898,
24 0x88c0, 0x88c1, 0x88d0, 0x88e3, 0x8900, 0x890c, 0x890f, 0x891a,
25 0x8c00, 0x8c01, 0x8c08, 0x8c10, 0x8c17, 0x8c1f, 0x8c26, 0x8c33,
29 0x88f0, 0x88f3, 0x890d, 0x890e, 0x8927, 0x8928, 0x8bf0, 0x8bf1,
30 0x8c02, 0x8c07, 0x8c11, 0x8c16, 0x8c20, 0x8c25,
34 0x9200, 0x9216, 0x9218, 0x9236, 0x9300, 0x9306,
[all …]
/linux/sound/pci/au88x0/
H A Dau8810.h11 #define NR_ADB 0x10
12 #define NR_WT 0x00
13 #define NR_SRC 0x10
14 #define NR_A3D 0x10
15 #define NR_MIXIN 0x20
16 #define NR_MIXOUT 0x10
20 #define VORTEX_ADBDMA_STAT 0x27e00 /* read only, subbuffer, DMA pos */
21 #define POS_MASK 0x00000fff
22 #define POS_SHIFT 0x0
23 #define ADB_SUBBUF_MASK 0x00003000 /* ADB only. */
[all …]
H A Dau8830.h18 #define NR_ADB 0x20
19 #define NR_SRC 0x10
20 #define NR_A3D 0x10
21 #define NR_MIXIN 0x20
22 #define NR_MIXOUT 0x10
23 #define NR_WT 0x40
26 #define VORTEX_ADBDMA_STAT 0x27e00 /* read only, subbuffer, DMA pos */
27 #define POS_MASK 0x00000fff
28 #define POS_SHIFT 0x0
29 #define ADB_SUBBUF_MASK 0x00003000 /* ADB only. */
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm-hr2.dtsi45 #size-cells = <0>;
47 cpu0: cpu@0 {
51 reg = <0x0>;
64 ranges = <0x00000000 0x19000000 0x00023000>;
68 a9pll: arm_clk@0 {
69 #clock-cells = <0>;
72 reg = <0x0 0x1000>;
77 reg = <0x20200 0x100>;
84 reg = <0x20600 0x20>;
92 reg = <0x20620 0x20>;
[all …]
H A Dbcm-ns.dtsi26 ranges = <0x00000000 0x18000000 0x00001000>;
32 reg = <0x0300 0x100>;
40 reg = <0x0400 0x100>;
44 pinctrl-0 = <&pinmux_uart1>;
51 ranges = <0x00000000 0x19000000 0x00023000>;
57 reg = <0x20000 0x100>;
62 reg = <0x20200 0x100>;
69 reg = <0x20600 0x20>;
78 #address-cells = <0>;
80 reg = <0x21000 0x1000>,
[all …]
/linux/Documentation/devicetree/bindings/mfd/
H A Dqcom,spmi-pmic.yaml30 - pattern: '^pm(a|s)?[0-9]*@.*$'
121 const: 0
136 "^adc@[0-9a-f]+$":
144 "^adc-tm@[0-9a-f]+$":
148 "^audio-codec@[0-9a-f]+$":
152 "^battery@[0-9a-f]+$":
157 "^charger@[0-9a-f]+$":
165 "gpio@[0-9a-f]+$":
169 "^haptics@[0-9a-f]+$":
173 "^led-controller@[0-9a-f]+$":
[all …]
/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_8_1_sm8450.h12 .max_mixer_blendstages = 0xb,
23 .base = 0x0, .len = 0x494,
25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
H A Ddpu_9_1_sar2130p.h12 .max_mixer_blendstages = 0xb,
23 .base = 0, .len = 0x494,
25 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
32 .base = 0x15000, .len = 0x290,
36 .base = 0x16000, .len = 0x290,
40 .base = 0x17000, .len = 0x290,
44 .base = 0x18000, .len = 0x290,
48 .base = 0x19000, .len = 0x290,
52 .base = 0x1a000, .len = 0x290,
60 .base = 0x4000, .len = 0x344,
[all …]
H A Ddpu_9_0_sm8550.h12 .max_mixer_blendstages = 0xb,
23 .base = 0, .len = 0x494,
25 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
32 .base = 0x15000, .len = 0x290,
36 .base = 0x16000, .len = 0x290,
40 .base = 0x17000, .len = 0x290,
44 .base = 0x18000, .len = 0x290,
48 .base = 0x19000, .len = 0x290,
52 .base = 0x1a000, .len = 0x290,
60 .base = 0x4000, .len = 0x344,
[all …]
H A Ddpu_8_4_sa8775p.h11 .max_mixer_blendstages = 0xb,
22 .base = 0x0, .len = 0x494,
24 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
25 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
28 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
29 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
H A Ddpu_8_0_sc8280xp.h23 .base = 0x0, .len = 0x494,
25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
33 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
[all …]
H A Ddpu_9_2_x1e80100.h11 .max_mixer_blendstages = 0xb,
22 .base = 0, .len = 0x494,
24 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
31 .base = 0x15000, .len = 0x290,
35 .base = 0x16000, .len = 0x290,
39 .base = 0x17000, .len = 0x290,
43 .base = 0x18000, .len = 0x290,
47 .base = 0x19000, .len = 0x290,
51 .base = 0x1a000, .len = 0x290,
59 .base = 0x4000, .len = 0x344,
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7996/
H A Dmmio.c20 #define INVALID_REG_ADDR 0xffffffff
23 [WF_AGG_BASE] = { { 0x820e2000, 0x820f2000, 0x830e2000 } },
24 [WF_ARB_BASE] = { { 0x820e3000, 0x820f3000, 0x830e3000 } },
25 [WF_TMAC_BASE] = { { 0x820e4000, 0x820f4000, 0x830e4000 } },
26 [WF_RMAC_BASE] = { { 0x820e5000, 0x820f5000, 0x830e5000 } },
27 [WF_DMA_BASE] = { { 0x820e7000, 0x820f7000, 0x830e7000 } },
28 [WF_WTBLOFF_BASE] = { { 0x820e9000, 0x820f9000, 0x830e9000 } },
29 [WF_ETBF_BASE] = { { 0x820ea000, 0x820fa000, 0x830ea000 } },
30 [WF_LPON_BASE] = { { 0x820eb000, 0x820fb000, 0x830eb000 } },
31 [WF_MIB_BASE] = { { 0x820ed000, 0x820fd000, 0x830ed000 } },
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap5-l4-abe.dtsi1 &l4_abe { /* 0x40100000 */
3 reg = <0x40100000 0x400>,
4 <0x40100400 0x400>;
10 ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
11 <0x49000000 0x49000000 0x100000>;
12 segment@0 { /* 0x40100000 */
18 <0x00000000 0x00000000 0x000400>, /* ap 0 */
19 <0x00000400 0x00000400 0x000400>, /* ap 1 */
20 <0x00022000 0x00022000 0x001000>, /* ap 2 */
21 <0x00023000 0x00023000 0x001000>, /* ap 3 */
[all …]

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