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/linux/arch/arc/include/asm/
H A Dperf_event.h15 #define ARC_REG_CC_BUILD 0xF6
16 #define ARC_REG_CC_INDEX 0x240
17 #define ARC_REG_CC_NAME0 0x241
18 #define ARC_REG_CC_NAME1 0x242
20 #define ARC_REG_PCT_BUILD 0xF5
21 #define ARC_REG_PCT_COUNTL 0x250
22 #define ARC_REG_PCT_COUNTH 0x251
23 #define ARC_REG_PCT_SNAPL 0x252
24 #define ARC_REG_PCT_SNAPH 0x253
25 #define ARC_REG_PCT_CONFIG 0x254
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Drenesas,rz-ssi.yaml65 bits[0:9] - Specifies MID/RID value of a SSI channel as below
66 MID/RID value of SSI rx0 = 0x256
67 MID/RID value of SSI tx0 = 0x255
68 MID/RID value of SSI rx1 = 0x25a
69 MID/RID value of SSI tx1 = 0x259
70 MID/RID value of SSI rt2 = 0x25f
71 MID/RID value of SSI rx3 = 0x262
72 MID/RID value of SSI tx3 = 0x261
75 bit[11] - LVL = 0, Detects based on the edge
77 bit[15] - TM = 0, Single transfer mode
[all …]
/linux/drivers/usb/serial/
H A Dsafe_serial.c35 * 0..N-2 data and optional padding
38 * bits 1-0 top two bits of 10 bit CRC
43 * + 7 . 6 . 5 . 4 . 3 . 2 . 1 . 0 | 7 . 6 . 5 . 4 . 3 . 2 . 1 . 0 +
85 module_param(safe, bool, 0);
88 module_param(padded, bool, 0);
91 #define CDC_DEVICE_CLASS 0x02
93 #define CDC_INTERFACE_CLASS 0x02
94 #define CDC_INTERFACE_SUBCLASS 0x06
96 #define LINEO_INTERFACE_CLASS 0xff
98 #define LINEO_INTERFACE_SUBCLASS_SAFENET 0x01
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/linux/drivers/gpu/drm/nouveau/dispnv04/
H A Dhw.h32 (0xffffffff >> (31 - ((1 ? field) - (0 ? field)))) << (0 ? field))
35 (((src) >> (srclowbit)) << (0 ? outfield)) & MASK(outfield))
137 /* CR57 and CR58 are a fun pair of regs. CR57 provides an index (0-0xf) for CR58
143 * 0x00 index to the appropriate dcb entry (or 7f for inactive)
144 * 0x02 dcb entry's "or" value (or 00 for inactive)
145 * 0x03 bit0 set for dual link (LVDS, possibly elsewhere too)
146 * 0x08 or 0x09 pxclk in MHz
147 * 0x0f laptop panel info - low nibble for PEXTDEV_BOOT_0 strap
198 nvif_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, enable ? 0 : 0x20); in NVSetEnablePalette()
205 return !(nvif_rd08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE) & 0x20); in NVGetEnablePalette()
[all …]
/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu7_ppsmc.h30 #define PPSMC_MSG_SetGBDroopSettings ((uint16_t) 0x305)
32 #define PPSMC_SWSTATE_FLAG_DC 0x01
33 #define PPSMC_SWSTATE_FLAG_UVD 0x02
34 #define PPSMC_SWSTATE_FLAG_VCE 0x04
36 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
37 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
38 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
40 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
41 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
42 #define PPSMC_SYSTEMFLAG_GDDR5 0x04
[all …]
H A Dtonga_ppsmc.h29 #define PPSMC_SWSTATE_FLAG_DC 0x01
30 #define PPSMC_SWSTATE_FLAG_UVD 0x02
31 #define PPSMC_SWSTATE_FLAG_VCE 0x04
32 #define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08
34 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
35 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
36 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
38 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
39 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
40 #define PPSMC_SYSTEMFLAG_GDDR5 0x04
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H A Dfiji_ppsmc.h30 #define PPSMC_SWSTATE_FLAG_DC 0x01
31 #define PPSMC_SWSTATE_FLAG_UVD 0x02
32 #define PPSMC_SWSTATE_FLAG_VCE 0x04
34 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
35 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
36 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
38 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
39 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
40 #define PPSMC_SYSTEMFLAG_GDDR5 0x04
42 #define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08
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/linux/drivers/video/fbdev/sis/
H A Dinitdef.h77 #define VB_SIS301 0x0001
78 #define VB_SIS301B 0x0002
79 #define VB_SIS302B 0x0004
80 #define VB_SIS301LV 0x0008
81 #define VB_SIS302LV 0x0010
82 #define VB_SIS302ELV 0x0020
83 #define VB_SIS301C 0x0040
84 #define VB_SIS307T 0x0080
85 #define VB_SIS307LV 0x0100
86 #define VB_UMC 0x4000
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H A Dinit301.c87 0x17,0x1d,0x03,0x09,0x05,0x06,0x0c,0x0c,
88 0x94,0x49,0x01,0x0a,0x06,0x0d,0x04,0x0a,
89 0x06,0x14,0x0d,0x04,0x0a,0x00,0x85,0x1b,
90 0x0c,0x50,0x00,0x97,0x00,0xda,0x4a,0x17,
91 0x7d,0x05,0x4b,0x00,0x00,0xe2,0x00,0x02,
92 0x03,0x0a,0x65,0x9d /*0x8d*/,0x08,0x92,0x8f,0x40,
93 0x60,0x80,0x14,0x90,0x8c,0x60,0x14,0x53 /*0x50*/,
94 0x00,0x40,0x44,0x00,0xdb,0x02,0x3b,0x00
97 0x33,0x06,0x06,0x09,0x0b,0x0c,0x0c,0x0c,
98 0x98,0x0a,0x01,0x0d,0x06,0x0d,0x04,0x0a,
[all …]
/linux/drivers/hwmon/
H A Dasb100.c23 * asb100 7 3 1 4 0x31 0x0694 yes no
41 static const unsigned short normal_i2c[] = { 0x2d, I2C_CLIENT_END };
44 module_param_array(force_subclients, short, NULL, 0);
48 /* Voltage IN registers 0-6 */
49 #define ASB100_REG_IN(nr) (0x20 + (nr))
50 #define ASB100_REG_IN_MAX(nr) (0x2b + (nr * 2))
51 #define ASB100_REG_IN_MIN(nr) (0x2c + (nr * 2))
54 #define ASB100_REG_FAN(nr) (0x28 + (nr))
55 #define ASB100_REG_FAN_MIN(nr) (0x3b + (nr))
58 static const u16 asb100_reg_temp[] = {0, 0x27, 0x150, 0x250, 0x17};
[all …]
H A Dw83627ehf.c24 * w83627ehf 10 5 4 3 0x8850 0x88 0x5ca3
25 * 0x8860 0xa1
26 * w83627dhg 9 5 4 3 0xa020 0xc1 0x5ca3
27 * w83627dhg-p 9 5 4 3 0xb070 0xc1 0x5ca3
28 * w83627uhg 8 2 2 3 0xa230 0xc1 0x5ca3
29 * w83667hg 9 5 3 3 0xa510 0xc1 0x5ca3
30 * w83667hg-b 9 5 3 4 0xb350 0xc1 0x5ca3
65 module_param(force_id, ushort, 0);
74 #define W83627EHF_LD_HWM 0x0b
75 #define W83667HG_LD_VID 0x0d
[all …]
H A Dnct6775-core.c22 * nct6106d 9 3 3 6+3 0xc450 0xc1 0x5ca3
23 * nct6116d 9 5 5 3+3 0xd280 0xc1 0x5ca3
24 * nct6775f 9 4 3 6+3 0xb470 0xc1 0x5ca3
25 * nct6776f 9 5 3 6+3 0xc330 0xc1 0x5ca3
26 * nct6779d 15 5 5 2+6 0xc560 0xc1 0x5ca3
27 * nct6791d 15 6 6 2+6 0xc800 0xc1 0x5ca3
28 * nct6792d 15 6 6 2+6 0xc910 0xc1 0x5ca3
29 * nct6793d 15 6 6 2+6 0xd120 0xc1 0x5ca3
30 * nct6795d 14 6 6 2+6 0xd350 0xc1 0x5ca3
31 * nct6796d 14 7 7 2+6 0xd420 0xc1 0x5ca3
[all …]
/linux/sound/drivers/opl4/
H A Dopl4_synth.c41 #define MIDI_CTL_RELEASE_TIME 0x48
42 #define MIDI_CTL_ATTACK_TIME 0x49
43 #define MIDI_CTL_DECAY_TIME 0x4b
44 #define MIDI_CTL_VIBRATO_RATE 0x4c
45 #define MIDI_CTL_VIBRATO_DEPTH 0x4d
46 #define MIDI_CTL_VIBRATO_DELAY 0x4e
52 static const s16 snd_opl4_pitch_map[0x600] = {
53 0x000,0x000,0x001,0x001,0x002,0x002,0x003,0x003,
54 0x004,0x004,0x005,0x005,0x006,0x006,0x006,0x007,
55 0x007,0x008,0x008,0x009,0x009,0x00a,0x00a,0x00b,
[all …]
/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_n.h11 #define B43_NPHY_BBCFG B43_PHY_N(0x001) /* BB config */
12 #define B43_NPHY_BBCFG_RSTCCA 0x4000 /* Reset CCA */
13 #define B43_NPHY_BBCFG_RSTRX 0x8000 /* Reset RX */
14 #define B43_NPHY_CHANNEL B43_PHY_N(0x005) /* Channel */
15 #define B43_NPHY_TXERR B43_PHY_N(0x007) /* TX error */
16 #define B43_NPHY_BANDCTL B43_PHY_N(0x009) /* Band control */
17 #define B43_NPHY_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */
18 #define B43_NPHY_4WI_ADDR B43_PHY_N(0x00B) /* Four-wire bus address */
19 #define B43_NPHY_4WI_DATAHI B43_PHY_N(0x00C) /* Four-wire bus data high */
20 #define B43_NPHY_4WI_DATALO B43_PHY_N(0x00D) /* Four-wire bus data low */
[all …]
/linux/include/drm/display/
H A Ddrm_dp.h44 #define DP_MSA_MISC_SYNC_CLOCK (1 << 0)
46 #define DP_MSA_MISC_STEREO_NO_3D (0 << 9)
50 #define DP_MSA_MISC_6_BPC (0 << 5)
66 #define DP_MSA_MISC_COLOR_RGB _DP_MSA_MISC_COLOR(0, 0, 0, 0)
67 #define DP_MSA_MISC_COLOR_CEA_RGB _DP_MSA_MISC_COLOR(0, 0, 1, 0)
68 #define DP_MSA_MISC_COLOR_RGB_WIDE_FIXED _DP_MSA_MISC_COLOR(0, 3, 0, 0)
69 #define DP_MSA_MISC_COLOR_RGB_WIDE_FLOAT _DP_MSA_MISC_COLOR(0, 3, 0, 1)
70 #define DP_MSA_MISC_COLOR_Y_ONLY _DP_MSA_MISC_COLOR(1, 0, 0, 0)
71 #define DP_MSA_MISC_COLOR_RAW _DP_MSA_MISC_COLOR(1, 1, 0, 0)
72 #define DP_MSA_MISC_COLOR_YCBCR_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 1, 0)
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/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dvegam_smumgr.c55 #define MC_CG_ARB_FREQ_F1 0x0b
60 #define PPSMC_MSG_ApplyAvfsCksOffVoltage ((uint16_t) 0x415)
61 #define PPSMC_MSG_EnableModeSwitchRLCNotification ((uint16_t) 0x305)
67 { 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
68 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61},
69 …{ 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5…
97 return 0; in vegam_smu_init()
102 int result = 0; in vegam_start_smu_in_protection_mode()
105 /* PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */ in vegam_start_smu_in_protection_mode()
112 if (result != 0) in vegam_start_smu_in_protection_mode()
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H A Diceland_smumgr.c62 #define ICELAND_SMC_SIZE 0x20000
65 #define MC_CG_ARB_FREQ_F1 0x0b
68 #define DEVICE_ID_VI_ICELAND_M_6900 0x6900
69 #define DEVICE_ID_VI_ICELAND_M_6901 0x6901
70 #define DEVICE_ID_VI_ICELAND_M_6902 0x6902
71 #define DEVICE_ID_VI_ICELAND_M_6903 0x6903
78 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
79 …{ 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D,…
80 …{ 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5…
91 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x0,
[all …]
H A Dpolaris10_smumgr.c55 #define POLARIS10_SMC_SIZE 0x20000
58 #define MC_CG_ARB_FREQ_F1 0x0b
63 { 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
64 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61},
65 …{ 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5…
83 …0x100ea446, 0x00, 0x03, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x30750000…
84 …0x400ea446, 0x01, 0x04, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x409c0000…
85 …0x740ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x50c30000…
86 …0xa40ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x60ea0000…
87 …0xd80ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x70110100…
[all …]
H A Dci_smumgr.c58 #define MC_CG_ARB_FREQ_F0 0x0a
59 #define MC_CG_ARB_FREQ_F1 0x0b
60 #define MC_CG_ARB_FREQ_F2 0x0c
61 #define MC_CG_ARB_FREQ_F3 0x0d
63 #define SMC_RAM_END 0x40000
69 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
70 …{ 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD,…
71 …{ 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9…
75 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
76 …{ 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD,…
[all …]
H A Dtonga_smumgr.c60 #define MC_CG_ARB_FREQ_F1 0x0b
68 {1, 0xF, 0xFD, 0x19,
69 5, 45, 0, 0xB0000,
70 {0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8,
71 0xC9, 0xC9, 0x2F, 0x4D, 0x61},
72 {0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203,
73 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4}
79 {600, 1050, 3, 0},
87 { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
91 /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] */
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/linux/drivers/gpu/drm/radeon/
H A Dci_dpm.c38 #define MC_CG_ARB_FREQ_F0 0x0a
39 #define MC_CG_ARB_FREQ_F1 0x0b
40 #define MC_CG_ARB_FREQ_F2 0x0c
41 #define MC_CG_ARB_FREQ_F3 0x0d
43 #define SMC_RAM_END 0x40000
50 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
51 …{ 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD,…
52 …{ 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9…
56 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
57 …{ 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD,…
[all …]