Lines Matching +full:0 +full:x255
38 #define MC_CG_ARB_FREQ_F0 0x0a
39 #define MC_CG_ARB_FREQ_F1 0x0b
40 #define MC_CG_ARB_FREQ_F2 0x0c
41 #define MC_CG_ARB_FREQ_F3 0x0d
43 #define SMC_RAM_END 0x40000
50 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
51 …{ 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD,…
52 …{ 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9…
56 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
57 …{ 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD,…
58 …{ 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9…
62 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
63 …{ 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D,…
64 …{ 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5…
68 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
69 …{ 0x8C, 0x247, 0x249, 0xA6, 0x80, 0x81, 0x8B, 0x89, 0x86, 0xC9, 0xCA, 0xC9, 0x4D, 0x4D,…
70 …{ 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9…
74 { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
75 { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
76 { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
77 { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
78 { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
79 { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
80 { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
81 { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
82 { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
83 { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
84 { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
85 { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
86 { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
87 { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
88 { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
89 { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
90 { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
91 { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
92 { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
93 { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
94 { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
95 { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
96 { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
97 { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
98 { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
99 { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
100 { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
101 { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
102 { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
103 { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
104 { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
105 { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
106 { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
107 { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
108 { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
109 { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
110 { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
111 { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
112 { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
113 { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
114 { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
115 { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
116 { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
117 { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
118 { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
119 { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
120 { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
121 { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
122 { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
123 { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
124 { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
125 { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
126 { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
127 { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
128 { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
129 { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
130 { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
131 { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
132 { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
133 { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
134 { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
135 { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
136 { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
137 { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
138 { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
139 { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
140 { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
141 { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
142 { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
143 { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
144 { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
145 { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
146 { 0xFFFFFFFF }
186 case 0x6649: in ci_initialize_powertune_defaults()
187 case 0x6650: in ci_initialize_powertune_defaults()
188 case 0x6651: in ci_initialize_powertune_defaults()
189 case 0x6658: in ci_initialize_powertune_defaults()
190 case 0x665C: in ci_initialize_powertune_defaults()
191 case 0x665D: in ci_initialize_powertune_defaults()
195 case 0x6640: in ci_initialize_powertune_defaults()
196 case 0x6641: in ci_initialize_powertune_defaults()
197 case 0x6646: in ci_initialize_powertune_defaults()
198 case 0x6647: in ci_initialize_powertune_defaults()
201 case 0x67B8: in ci_initialize_powertune_defaults()
202 case 0x67B0: in ci_initialize_powertune_defaults()
205 case 0x67BA: in ci_initialize_powertune_defaults()
206 case 0x67B1: in ci_initialize_powertune_defaults()
209 case 0x67A0: in ci_initialize_powertune_defaults()
210 case 0x67A1: in ci_initialize_powertune_defaults()
211 case 0x67A2: in ci_initialize_powertune_defaults()
212 case 0x67A8: in ci_initialize_powertune_defaults()
213 case 0x67A9: in ci_initialize_powertune_defaults()
214 case 0x67AA: in ci_initialize_powertune_defaults()
215 case 0x67B9: in ci_initialize_powertune_defaults()
216 case 0x67BE: in ci_initialize_powertune_defaults()
221 pi->dte_tj_offset = 0; in ci_initialize_powertune_defaults()
262 for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) { in ci_populate_bapm_vddc_vid_sidd()
272 return 0; in ci_populate_bapm_vddc_vid_sidd()
284 for (i = 0; i < pi->vddc_voltage_table.count; i++) in ci_populate_vddc_vid()
287 return 0; in ci_populate_vddc_vid()
298 pi->smc_powertune_table.SviLoadLineOffsetVddC = 0; in ci_populate_svi_load_line()
300 return 0; in ci_populate_svi_load_line()
315 return 0; in ci_populate_tdc_limit()
335 return 0; in ci_populate_dw8()
343 (rdev->pm.dpm.fan.fan_output_sensitivity == 0)) in ci_populate_fuzzy_fan()
350 return 0; in ci_populate_fuzzy_fan()
360 min = max = hi_vid[0]; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
361 for (i = 0; i < 8; i++) { in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
362 if (0 != hi_vid[i]) { in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
369 if (0 != lo_vid[i]) { in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
377 if ((min == 0) || (max == 0)) in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
382 return 0; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
398 return 0; in ci_populate_bapm_vddc_base_leakage_sidd()
427 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0); in ci_populate_bapm_parameters_in_dpm_table()
428 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0); in ci_populate_bapm_parameters_in_dpm_table()
435 for (i = 0; i < SMU7_DTE_ITERATIONS; i++) { in ci_populate_bapm_parameters_in_dpm_table()
436 for (j = 0; j < SMU7_DTE_SOURCES; j++) { in ci_populate_bapm_parameters_in_dpm_table()
437 for (k = 0; k < SMU7_DTE_SINKS; k++) { in ci_populate_bapm_parameters_in_dpm_table()
446 return 0; in ci_populate_bapm_parameters_in_dpm_table()
493 return 0; in ci_populate_pm_base()
543 u32 cache = 0; in ci_program_pt_config_registers()
548 while (config_regs->offset != 0xFFFFFFFF) { in ci_program_pt_config_registers()
579 cache = 0; in ci_program_pt_config_registers()
583 return 0; in ci_program_pt_config_registers()
608 return 0; in ci_enable_didt()
615 int ret = 0; in ci_enable_power_containment()
618 pi->power_containment_features = 0; in ci_enable_power_containment()
662 pi->power_containment_features = 0; in ci_enable_power_containment()
673 int ret = 0; in ci_enable_smc_cac()
707 return 0; in ci_enable_thermal_based_sclk_dpm()
719 int ret = 0; in ci_power_control_set_level()
779 rps->evclk = 0; in ci_apply_state_adjust_rules()
780 rps->ecclk = 0; in ci_apply_state_adjust_rules()
800 for (i = 0; i < ps->performance_level_count; i++) { in ci_apply_state_adjust_rules()
812 sclk = ps->performance_levels[0].sclk; in ci_apply_state_adjust_rules()
814 mclk = ps->performance_levels[0].mclk; in ci_apply_state_adjust_rules()
815 sclk = ps->performance_levels[0].sclk; in ci_apply_state_adjust_rules()
825 ps->performance_levels[0].sclk = sclk; in ci_apply_state_adjust_rules()
826 ps->performance_levels[0].mclk = mclk; in ci_apply_state_adjust_rules()
828 if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk) in ci_apply_state_adjust_rules()
829 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk; in ci_apply_state_adjust_rules()
832 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk) in ci_apply_state_adjust_rules()
833 ps->performance_levels[0].mclk = ps->performance_levels[1].mclk; in ci_apply_state_adjust_rules()
835 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk) in ci_apply_state_adjust_rules()
836 ps->performance_levels[1].mclk = ps->performance_levels[0].mclk; in ci_apply_state_adjust_rules()
843 int low_temp = 0 * 1000; in ci_thermal_set_temperature_range()
862 #if 0 in ci_thermal_set_temperature_range()
873 return 0; in ci_thermal_set_temperature_range()
902 return 0; in ci_thermal_enable_alert()
919 tmp |= TMIN(0); in ci_fan_ctrl_set_static_mode()
940 return 0; in ci_thermal_setup_fan_table()
945 if (duty100 == 0) { in ci_thermal_setup_fan_table()
947 return 0; in ci_thermal_setup_fan_table()
1001 return 0; in ci_thermal_setup_fan_table()
1029 return 0; in ci_fan_ctrl_start_smc_fan_control()
1040 return 0; in ci_fan_ctrl_stop_smc_fan_control()
1057 if (duty100 == 0) in ci_fan_ctrl_get_fan_speed_percent()
1067 return 0; in ci_fan_ctrl_get_fan_speed_percent()
1089 if (duty100 == 0) in ci_fan_ctrl_set_fan_speed_percent()
1100 return 0; in ci_fan_ctrl_set_fan_speed_percent()
1125 return 0; in ci_fan_ctrl_get_mode()
1131 #if 0
1141 if (rdev->pm.fan_pulses_per_revolution == 0)
1145 if (tach_period == 0)
1150 return 0;
1162 if (rdev->pm.fan_pulses_per_revolution == 0)
1179 return 0;
1219 tmp |= TACH_PWM_RESP_RATE(0x28); in ci_thermal_initialize()
1241 return 0; in ci_thermal_start_thermal_controller()
1250 #if 0
1291 int ret = 0; in ci_update_sclk_t()
1292 u32 low_sclk_interrupt_t = 0; in ci_update_sclk_t()
1315 pi->vddc_leakage.count = 0; in ci_get_leakage_voltages()
1316 pi->vddci_leakage.count = 0; in ci_get_leakage_voltages()
1319 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) { in ci_get_leakage_voltages()
1321 if (radeon_atom_get_voltage_evv(rdev, virtual_voltage_id, &vddc) != 0) in ci_get_leakage_voltages()
1323 if (vddc != 0 && vddc != virtual_voltage_id) { in ci_get_leakage_voltages()
1329 } else if (radeon_atom_get_leakage_id_from_vbios(rdev, &leakage_id) == 0) { in ci_get_leakage_voltages()
1330 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) { in ci_get_leakage_voltages()
1334 leakage_id) == 0) { in ci_get_leakage_voltages()
1335 if (vddc != 0 && vddc != virtual_voltage_id) { in ci_get_leakage_voltages()
1340 if (vddci != 0 && vddci != virtual_voltage_id) { in ci_get_leakage_voltages()
1357 case 0: in ci_set_dpm_event_sources()
1418 return 0; in ci_unfreeze_sclk_mclk_dpm()
1434 pi->need_update_smu7_dpm_table = 0; in ci_unfreeze_sclk_mclk_dpm()
1435 return 0; in ci_unfreeze_sclk_mclk_dpm()
1457 WREG32_SMC(LCAC_MC0_CNTL, 0x05); in ci_enable_sclk_mclk_dpm()
1458 WREG32_SMC(LCAC_MC1_CNTL, 0x05); in ci_enable_sclk_mclk_dpm()
1459 WREG32_SMC(LCAC_CPL_CNTL, 0x100005); in ci_enable_sclk_mclk_dpm()
1463 WREG32_SMC(LCAC_MC0_CNTL, 0x400005); in ci_enable_sclk_mclk_dpm()
1464 WREG32_SMC(LCAC_MC1_CNTL, 0x400005); in ci_enable_sclk_mclk_dpm()
1465 WREG32_SMC(LCAC_CPL_CNTL, 0x500005); in ci_enable_sclk_mclk_dpm()
1481 return 0; in ci_enable_sclk_mclk_dpm()
1499 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000); in ci_start_dpm()
1501 WREG32_P(BIF_LNCNT_RESET, 0, ~RESET_LNCNT_EN); in ci_start_dpm()
1517 return 0; in ci_start_dpm()
1526 return 0; in ci_freeze_sclk_mclk_dpm()
1542 return 0; in ci_freeze_sclk_mclk_dpm()
1574 return 0; in ci_stop_dpm()
1588 #if 0
1611 return 0;
1625 for (i = 0; i < rdev->usec_timeout; i++) { in ci_send_msg_to_smc()
1627 if (tmp != 0) in ci_send_msg_to_smc()
1667 return 0; in ci_dpm_force_state_sclk()
1681 return 0; in ci_dpm_force_state_mclk()
1695 return 0; in ci_dpm_force_state_pcie()
1709 return 0; in ci_set_power_limit()
1719 return 0; in ci_set_overdrive_target_tdp()
1722 #if 0
1737 sclk_freq = 0; in ci_get_average_sclk_freq()
1750 mclk_freq = 0; in ci_get_average_mclk_freq()
1762 for (i = 0; i < rdev->usec_timeout; i++) { in ci_dpm_start_smc()
1825 return 0; in ci_process_firmware_header()
1859 pi->low_sclk_interrupt_t = 0; in ci_init_sclk_t()
1883 #if 0
1891 return 0;
1902 for (i = 0; i < rdev->usec_timeout; i++) {
1908 return 0;
1917 return (ci_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 0 : -EINVAL; in ci_notify_smc_display_change()
1940 return 0; in ci_enable_ds_master_switch()
1953 if (rdev->pm.dpm.new_active_crtc_count > 0) in ci_program_display_gap()
1959 if (refresh_rate == 0) in ci_program_display_gap()
1961 if (vblank_time == 0xffffffff) in ci_program_display_gap()
1969 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64); in ci_program_display_gap()
2041 WREG32_SMC(CG_FTV_0, 0); in ci_clear_vc()
2042 WREG32_SMC(CG_FTV_1, 0); in ci_clear_vc()
2043 WREG32_SMC(CG_FTV_2, 0); in ci_clear_vc()
2044 WREG32_SMC(CG_FTV_3, 0); in ci_clear_vc()
2045 WREG32_SMC(CG_FTV_4, 0); in ci_clear_vc()
2046 WREG32_SMC(CG_FTV_5, 0); in ci_clear_vc()
2047 WREG32_SMC(CG_FTV_6, 0); in ci_clear_vc()
2048 WREG32_SMC(CG_FTV_7, 0); in ci_clear_vc()
2056 for (i = 0; i < rdev->usec_timeout; i++) { in ci_upload_firmware()
2078 voltage_table->mask_low = 0; in ci_get_svi2_voltage_table()
2079 voltage_table->phase_delay = 0; in ci_get_svi2_voltage_table()
2082 for (i = 0; i < voltage_table->count; i++) { in ci_get_svi2_voltage_table()
2084 voltage_table->entries[i].smio_low = 0; in ci_get_svi2_voltage_table()
2087 return 0; in ci_get_svi2_voltage_table()
2149 return 0; in ci_construct_voltage_tables()
2181 for (count = 0; count < table->VddcLevelCount; count++) { in ci_populate_smc_vddc_table()
2190 table->VddcLevel[count].Smio = 0; in ci_populate_smc_vddc_table()
2194 return 0; in ci_populate_smc_vddc_table()
2204 for (count = 0; count < table->VddciLevelCount; count++) { in ci_populate_smc_vddci_table()
2213 table->VddciLevel[count].Smio = 0; in ci_populate_smc_vddci_table()
2217 return 0; in ci_populate_smc_vddci_table()
2227 for (count = 0; count < table->MvddLevelCount; count++) { in ci_populate_smc_mvdd_table()
2236 table->MvddLevel[count].Smio = 0; in ci_populate_smc_mvdd_table()
2240 return 0; in ci_populate_smc_mvdd_table()
2260 return 0; in ci_populate_smc_voltage_tables()
2267 u32 i = 0; in ci_populate_mvdd_value()
2270 for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) { in ci_populate_mvdd_value()
2297 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in ci_get_std_voltage_value_sidd()
2314 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in ci_get_std_voltage_value_sidd()
2332 return 0; in ci_get_std_voltage_value_sidd()
2344 for (i = 0; i < limits->count; i++) { in ci_populate_phase_value_based_on_sclk()
2361 for (i = 0; i < limits->count; i++) { in ci_populate_phase_value_based_on_mclk()
2380 tmp &= 0x00FFFFFF; in ci_init_arb_table_index()
2391 u32 i = 0; in ci_get_dependency_volt_by_clk()
2393 if (allowed_clock_voltage_table->count == 0) in ci_get_dependency_volt_by_clk()
2396 for (i = 0; i < allowed_clock_voltage_table->count; i++) { in ci_get_dependency_volt_by_clk()
2399 return 0; in ci_get_dependency_volt_by_clk()
2405 return 0; in ci_get_dependency_volt_by_clk()
2417 return 0; in ci_get_sleep_divider_id_from_clock()
2421 if (tmp >= min || i == 0) in ci_get_sleep_divider_id_from_clock()
2436 0 : -EINVAL; in ci_reset_to_default()
2443 tmp = (RREG32_SMC(SMC_SCRATCH9) & 0x0000ff00) >> 8; in ci_force_switch_to_arb_f0()
2446 return 0; in ci_force_switch_to_arb_f0()
2460 patch = ((tmp & 0x0000f00) == 0x300) ? true : false; in ci_register_patching_mc_arb()
2463 ((rdev->pdev->device == 0x67B0) || in ci_register_patching_mc_arb()
2464 (rdev->pdev->device == 0x67B1))) { in ci_register_patching_mc_arb()
2466 tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff; in ci_register_patching_mc_arb()
2467 *dram_timimg2 &= ~0x00ff0000; in ci_register_patching_mc_arb()
2470 tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff; in ci_register_patching_mc_arb()
2471 *dram_timimg2 &= ~0x00ff0000; in ci_register_patching_mc_arb()
2499 return 0; in ci_populate_memory_timing_parameters()
2507 int ret = 0; in ci_do_program_memory_timing_parameters()
2509 memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable)); in ci_do_program_memory_timing_parameters()
2511 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) { in ci_do_program_memory_timing_parameters()
2512 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) { in ci_do_program_memory_timing_parameters()
2522 if (ret == 0) in ci_do_program_memory_timing_parameters()
2536 if (pi->need_update_smu7_dpm_table == 0) in ci_program_memory_timing_parameters()
2537 return 0; in ci_program_memory_timing_parameters()
2547 u32 level = 0; in ci_populate_smc_initial_state()
2549 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) { in ci_populate_smc_initial_state()
2551 boot_state->performance_levels[0].sclk) { in ci_populate_smc_initial_state()
2557 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) { in ci_populate_smc_initial_state()
2559 boot_state->performance_levels[0].mclk) { in ci_populate_smc_initial_state()
2569 u32 mask_value = 0; in ci_get_dpm_level_enable_mask_value()
2571 for (i = dpm_table->count; i > 0; i--) { in ci_get_dpm_level_enable_mask_value()
2574 mask_value |= 0x1; in ci_get_dpm_level_enable_mask_value()
2576 mask_value &= 0xFFFFFFFE; in ci_get_dpm_level_enable_mask_value()
2589 for (i = 0; i < dpm_table->pcie_speed_table.count; i++) { in ci_populate_smc_link_level()
2614 for (count = 0; count < table->UvdLevelCount; count++) { in ci_populate_smc_uvd_level()
2657 for (count = 0; count < table->VceLevelCount; count++) { in ci_populate_smc_vce_level()
2690 for (count = 0; count < table->AcpLevelCount; count++) { in ci_populate_smc_acp_level()
2722 for (count = 0; count < table->SamuLevelCount; count++) { in ci_populate_smc_samu_level()
2828 return 0; in ci_calculate_mclk_params()
2872 memory_level->UpH = 0; in ci_populate_single_memory_level()
2874 memory_level->VoltageDownH = 0; in ci_populate_single_memory_level()
2909 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) in ci_populate_single_memory_level()
2910 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; in ci_populate_single_memory_level()
2912 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; in ci_populate_single_memory_level()
2918 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; in ci_populate_single_memory_level()
2942 return 0; in ci_populate_single_memory_level()
2964 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1; in ci_populate_smc_acpi_level()
2976 table->ACPILevel.DeepSleepDivId = 0; in ci_populate_smc_acpi_level()
2990 table->ACPILevel.CcPwrDynRm = 0; in ci_populate_smc_acpi_level()
2991 table->ACPILevel.CcPwrDynRm1 = 0; in ci_populate_smc_acpi_level()
3017 if (ci_populate_mvdd_value(rdev, 0, &voltage_level)) in ci_populate_smc_acpi_level()
3018 table->MemoryACPILevel.MinMvdd = 0; in ci_populate_smc_acpi_level()
3043 table->MemoryACPILevel.EnabledForThrottle = 0; in ci_populate_smc_acpi_level()
3044 table->MemoryACPILevel.EnabledForActivity = 0; in ci_populate_smc_acpi_level()
3045 table->MemoryACPILevel.UpH = 0; in ci_populate_smc_acpi_level()
3047 table->MemoryACPILevel.VoltageDownH = 0; in ci_populate_smc_acpi_level()
3057 return 0; in ci_populate_smc_acpi_level()
3069 0 : -EINVAL; in ci_enable_ulv()
3072 0 : -EINVAL; in ci_enable_ulv()
3075 return 0; in ci_enable_ulv()
3084 state->CcPwrDynRm = 0; in ci_populate_ulv_level()
3085 state->CcPwrDynRm1 = 0; in ci_populate_ulv_level()
3087 if (ulv_voltage == 0) { in ci_populate_ulv_level()
3089 return 0; in ci_populate_ulv_level()
3093 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) in ci_populate_ulv_level()
3094 state->VddcOffset = 0; in ci_populate_ulv_level()
3097 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage; in ci_populate_ulv_level()
3099 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) in ci_populate_ulv_level()
3100 state->VddcOffsetVid = 0; in ci_populate_ulv_level()
3103 ((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) * in ci_populate_ulv_level()
3106 state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1; in ci_populate_ulv_level()
3112 return 0; in ci_populate_ulv_level()
3137 fbdiv = dividers.fb_div & 0x3FFFFFF; in ci_calculate_sclk_params()
3168 return 0; in ci_calculate_sclk_params()
3191 graphic_level->Flags = 0; in ci_populate_single_graphic_level()
3202 graphic_level->CcPwrDynRm = 0; in ci_populate_single_graphic_level()
3203 graphic_level->CcPwrDynRm1 = 0; in ci_populate_single_graphic_level()
3205 graphic_level->UpH = 0; in ci_populate_single_graphic_level()
3206 graphic_level->DownH = 0; in ci_populate_single_graphic_level()
3207 graphic_level->VoltageDownH = 0; in ci_populate_single_graphic_level()
3208 graphic_level->PowerThrottle = 0; in ci_populate_single_graphic_level()
3229 return 0; in ci_populate_single_graphic_level()
3243 memset(levels, 0, level_array_size); in ci_populate_all_graphic_levels()
3245 for (i = 0; i < dpm_table->sclk_table.count; i++) { in ci_populate_all_graphic_levels()
3253 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in ci_populate_all_graphic_levels()
3258 pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in ci_populate_all_graphic_levels()
3270 return 0; in ci_populate_all_graphic_levels()
3290 memset(levels, 0, level_array_size); in ci_populate_all_memory_levels()
3292 for (i = 0; i < dpm_table->mclk_table.count; i++) { in ci_populate_all_memory_levels()
3293 if (dpm_table->mclk_table.dpm_levels[i].value == 0) in ci_populate_all_memory_levels()
3302 pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; in ci_populate_all_memory_levels()
3305 ((rdev->pdev->device == 0x67B0) || (rdev->pdev->device == 0x67B1))) { in ci_populate_all_memory_levels()
3307 pi->smc_state_table.MemoryLevel[0].MinVddc; in ci_populate_all_memory_levels()
3309 pi->smc_state_table.MemoryLevel[0].MinVddcPhases; in ci_populate_all_memory_levels()
3312 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F); in ci_populate_all_memory_levels()
3327 return 0; in ci_populate_all_memory_levels()
3337 for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++) in ci_reset_single_dpm_table()
3369 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, in ci_setup_default_pcie_tables()
3373 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, in ci_setup_default_pcie_tables()
3394 return 0; in ci_setup_default_pcie_tables()
3417 memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table)); in ci_setup_default_dpm_tables()
3435 pi->dpm_table.sclk_table.count = 0; in ci_setup_default_dpm_tables()
3436 for (i = 0; i < allowed_sclk_vddc_table->count; i++) { in ci_setup_default_dpm_tables()
3437 if ((i == 0) || in ci_setup_default_dpm_tables()
3443 (i == 0) ? true : false; in ci_setup_default_dpm_tables()
3448 pi->dpm_table.mclk_table.count = 0; in ci_setup_default_dpm_tables()
3449 for (i = 0; i < allowed_mclk_table->count; i++) { in ci_setup_default_dpm_tables()
3450 if ((i == 0) || in ci_setup_default_dpm_tables()
3456 (i == 0) ? true : false; in ci_setup_default_dpm_tables()
3461 for (i = 0; i < allowed_sclk_vddc_table->count; i++) { in ci_setup_default_dpm_tables()
3472 for (i = 0; i < allowed_mclk_table->count; i++) { in ci_setup_default_dpm_tables()
3482 for (i = 0; i < allowed_mclk_table->count; i++) { in ci_setup_default_dpm_tables()
3492 return 0; in ci_setup_default_dpm_tables()
3501 for (i = 0; i < table->count; i++) { in ci_find_boot_level()
3504 ret = 0; in ci_find_boot_level()
3578 table->UvdBootLevel = 0; in ci_init_smc_table()
3579 table->VceBootLevel = 0; in ci_init_smc_table()
3580 table->AcpBootLevel = 0; in ci_init_smc_table()
3581 table->SamuBootLevel = 0; in ci_init_smc_table()
3582 table->GraphicsBootLevel = 0; in ci_init_smc_table()
3583 table->MemoryBootLevel = 0; in ci_init_smc_table()
3618 table->VoltageResponseTime = 0; in ci_init_smc_table()
3620 table->PhaseResponseTime = 0; in ci_init_smc_table()
3627 table->SVI2Enable = 0; in ci_init_smc_table()
3630 table->SclkStepSize = 0x4000; in ci_init_smc_table()
3656 return 0; in ci_init_smc_table()
3665 for (i = 0; i < dpm_table->count; i++) { in ci_trim_single_dpm_states()
3682 for (i = 0; i < pcie_table->count; i++) { in ci_trim_pcie_dpm_states()
3692 for (i = 0; i < pcie_table->count; i++) { in ci_trim_pcie_dpm_states()
3716 high_limit_count = 0; in ci_trim_dpm_states()
3722 state->performance_levels[0].sclk, in ci_trim_dpm_states()
3727 state->performance_levels[0].mclk, in ci_trim_dpm_states()
3731 state->performance_levels[0].pcie_gen, in ci_trim_dpm_states()
3732 state->performance_levels[0].pcie_lane, in ci_trim_dpm_states()
3736 return 0; in ci_trim_dpm_states()
3745 u32 requested_voltage = 0; in ci_apply_disp_minimum_voltage_request()
3753 for (i = 0; i < disp_voltage_table->count; i++) { in ci_apply_disp_minimum_voltage_request()
3758 for (i = 0; i < vddc_table->count; i++) { in ci_apply_disp_minimum_voltage_request()
3764 0 : -EINVAL; in ci_apply_disp_minimum_voltage_request()
3797 #if 0 in ci_upload_dpm_level_enable_mask()
3808 return 0; in ci_upload_dpm_level_enable_mask()
3822 pi->need_update_smu7_dpm_table = 0; in ci_find_dpm_states_clocks_in_dpm_table()
3824 for (i = 0; i < sclk_table->count; i++) { in ci_find_dpm_states_clocks_in_dpm_table()
3840 for (i = 0; i < mclk_table->count; i++) { in ci_find_dpm_states_clocks_in_dpm_table()
3864 return 0; in ci_populate_and_upload_sclk_mclk_dpm_levels()
3884 return 0; in ci_populate_and_upload_sclk_mclk_dpm_levels()
3899 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0; in ci_enable_uvd_dpm()
3901 for (i = rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) { in ci_enable_uvd_dpm()
3914 if (pi->last_mclk_dpm_enable_mask & 0x1) { in ci_enable_uvd_dpm()
3916 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; in ci_enable_uvd_dpm()
3922 if (pi->last_mclk_dpm_enable_mask & 0x1) { in ci_enable_uvd_dpm()
3933 0 : -EINVAL; in ci_enable_uvd_dpm()
3948 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0; in ci_enable_vce_dpm()
3949 for (i = rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) { in ci_enable_vce_dpm()
3965 0 : -EINVAL; in ci_enable_vce_dpm()
3968 #if 0
3981 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
3982 for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3997 0 : -EINVAL;
4012 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
4013 for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4029 0 : -EINVAL;
4040 (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0)) in ci_update_uvd_dpm()
4041 pi->smc_state_table.UvdBootLevel = 0; in ci_update_uvd_dpm()
4062 for (i = 0; i < table->count; i++) { in ci_get_vce_boot_level()
4075 int ret = 0; in ci_update_vce_dpm()
4100 #if 0
4112 pi->smc_state_table.AcpBootLevel = 0;
4142 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; in ci_generate_dpm_level_enable_mask()
4147 return 0; in ci_generate_dpm_level_enable_mask()
4153 u32 level = 0; in ci_get_lowest_enabled_level()
4155 while ((level_mask & (1 << level)) == 0) in ci_get_lowest_enabled_level()
4172 levels = 0; in ci_dpm_force_performance_level()
4180 for (i = 0; i < rdev->usec_timeout; i++) { in ci_dpm_force_performance_level()
4191 levels = 0; in ci_dpm_force_performance_level()
4199 for (i = 0; i < rdev->usec_timeout; i++) { in ci_dpm_force_performance_level()
4210 levels = 0; in ci_dpm_force_performance_level()
4218 for (i = 0; i < rdev->usec_timeout; i++) { in ci_dpm_force_performance_level()
4235 for (i = 0; i < rdev->usec_timeout; i++) { in ci_dpm_force_performance_level()
4250 for (i = 0; i < rdev->usec_timeout; i++) { in ci_dpm_force_performance_level()
4265 for (i = 0; i < rdev->usec_timeout; i++) { in ci_dpm_force_performance_level()
4289 return 0; in ci_dpm_force_performance_level()
4299 for (i = 0, j = table->last; i < table->last; i++) { in ci_set_mc_special_registers()
4307 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
4309 ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); in ci_set_mc_special_registers()
4318 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
4320 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); in ci_set_mc_special_registers()
4322 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; in ci_set_mc_special_registers()
4331 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
4333 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; in ci_set_mc_special_registers()
4344 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
4346 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); in ci_set_mc_special_registers()
4360 return 0; in ci_set_mc_special_registers()
4440 for (i = 0; i < table->last; i++) { in ci_set_valid_flag()
4456 for (i = 0; i < table->last; i++) { in ci_set_s0_mc_reg_index()
4473 for (i = 0; i < table->last; i++) in ci_copy_vbios_mc_reg_table()
4478 for (i = 0; i < table->num_entries; i++) { in ci_copy_vbios_mc_reg_table()
4481 for (j = 0; j < table->last; j++) in ci_copy_vbios_mc_reg_table()
4487 return 0; in ci_copy_vbios_mc_reg_table()
4498 patch = ((tmp & 0x0000f00) == 0x300) ? true : false; in ci_register_patching_mc_seq()
4501 ((rdev->pdev->device == 0x67B0) || in ci_register_patching_mc_seq()
4502 (rdev->pdev->device == 0x67B1))) { in ci_register_patching_mc_seq()
4503 for (i = 0; i < table->last; i++) { in ci_register_patching_mc_seq()
4508 for (k = 0; k < table->num_entries; k++) { in ci_register_patching_mc_seq()
4512 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) | in ci_register_patching_mc_seq()
4513 0x00000007; in ci_register_patching_mc_seq()
4517 for (k = 0; k < table->num_entries; k++) { in ci_register_patching_mc_seq()
4521 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) | in ci_register_patching_mc_seq()
4522 0x0000D0DD; in ci_register_patching_mc_seq()
4526 for (k = 0; k < table->num_entries; k++) { in ci_register_patching_mc_seq()
4530 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) | in ci_register_patching_mc_seq()
4531 0x0000D0DD; in ci_register_patching_mc_seq()
4535 for (k = 0; k < table->num_entries; k++) { in ci_register_patching_mc_seq()
4538 table->mc_reg_table_entry[k].mc_data[i] = 0; in ci_register_patching_mc_seq()
4542 for (k = 0; k < table->num_entries; k++) { in ci_register_patching_mc_seq()
4545 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) | in ci_register_patching_mc_seq()
4546 0x000C0140; in ci_register_patching_mc_seq()
4549 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) | in ci_register_patching_mc_seq()
4550 0x000C0150; in ci_register_patching_mc_seq()
4554 for (k = 0; k < table->num_entries; k++) { in ci_register_patching_mc_seq()
4557 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) | in ci_register_patching_mc_seq()
4558 0x00000030; in ci_register_patching_mc_seq()
4561 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) | in ci_register_patching_mc_seq()
4562 0x00000035; in ci_register_patching_mc_seq()
4572 tmp = (tmp & 0xFFF8FFFF) | (1 << 16); in ci_register_patching_mc_seq()
4577 return 0; in ci_register_patching_mc_seq()
4645 for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) { in ci_populate_mc_reg_addresses()
4657 return 0; in ci_populate_mc_reg_addresses()
4666 for (i = 0, j = 0; j < num_entries; j++) { in ci_convert_mc_registers()
4679 u32 i = 0; in ci_convert_mc_reg_table_entry_to_smc()
4681 for (i = 0; i < pi->mc_reg_table.num_entries; i++) { in ci_convert_mc_reg_table_entry_to_smc()
4686 if ((i == pi->mc_reg_table.num_entries) && (i > 0)) in ci_convert_mc_reg_table_entry_to_smc()
4700 for (i = 0; i < pi->dpm_table.mclk_table.count; i++) in ci_convert_mc_reg_table_to_smc()
4711 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); in ci_populate_initial_mc_reg_table()
4730 return 0; in ci_update_and_upload_mc_reg_table()
4732 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); in ci_update_and_upload_mc_reg_table()
4738 offsetof(SMU7_Discrete_MCRegisters, data[0]), in ci_update_and_upload_mc_reg_table()
4739 (u8 *)&pi->smc_mc_reg_table.data[0], in ci_update_and_upload_mc_reg_table()
4758 u16 pcie_speed, max_speed = 0; in ci_get_maximum_link_speed()
4760 for (i = 0; i < state->performance_level_count; i++) { in ci_get_maximum_link_speed()
4771 u32 speed_cntl = 0; in ci_get_current_pcie_speed()
4781 u32 link_width = 0; in ci_get_current_pcie_lane_number()
4825 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) in ci_request_link_speed_change_before_state_change()
4832 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) in ci_request_link_speed_change_before_state_change()
4864 (ci_get_current_pcie_speed(rdev) > 0)) in ci_notify_link_speed_change_after_state_change()
4896 pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v; in ci_set_private_data_variables_based_on_pptable()
4900 pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v; in ci_set_private_data_variables_based_on_pptable()
4913 return 0; in ci_set_private_data_variables_based_on_pptable()
4922 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) { in ci_patch_with_vddc_leakage()
4936 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) { in ci_patch_with_vddci_leakage()
4950 for (i = 0; i < table->count; i++) in ci_patch_clock_voltage_dependency_table_with_vddc_leakage()
4961 for (i = 0; i < table->count; i++) in ci_patch_clock_voltage_dependency_table_with_vddci_leakage()
4972 for (i = 0; i < table->count; i++) in ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage()
4983 for (i = 0; i < table->count; i++) in ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage()
4994 for (i = 0; i < table->count; i++) in ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage()
5014 for (i = 0; i < table->count; i++) in ci_patch_cac_leakage_table_with_vddc_leakage()
5096 return 0; in ci_dpm_pre_set_power_state()
5243 return 0; in ci_dpm_enable()
5273 return 0; in ci_dpm_late_enable()
5369 return 0; in ci_dpm_set_power_state()
5372 #if 0
5420 rps->vclk = 0; in ci_parse_pplib_non_clock_info()
5421 rps->dclk = 0; in ci_parse_pplib_non_clock_info()
5538 rdev->pm.dpm.num_ps = 0; in ci_parse_power_table()
5539 for (i = 0; i < state_array->ucNumEntries; i++) { in ci_parse_power_table()
5558 k = 0; in ci_parse_power_table()
5559 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; in ci_parse_power_table()
5560 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { in ci_parse_power_table()
5567 ((u8 *)&clock_info_array->clockInfo[0] + in ci_parse_power_table()
5579 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) { in ci_parse_power_table()
5592 return 0; in ci_parse_power_table()
5595 for (i = 0; i < rdev->pm.dpm.num_ps; i++) in ci_parse_power_table()
5623 return 0; in ci_get_vbios_boot_values()
5632 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { in ci_dpm_fini()
5661 pi->sys_pcie_mask = 0; in ci_dpm_init()
5680 pi->pcie_lane_performance.max = 0; in ci_dpm_init()
5682 pi->pcie_lane_powersaving.max = 0; in ci_dpm_init()
5713 pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5724 pi->sclk_dpm_key_disabled = 0; in ci_dpm_init()
5725 pi->mclk_dpm_key_disabled = 0; in ci_dpm_init()
5726 pi->pcie_dpm_key_disabled = 0; in ci_dpm_init()
5727 pi->thermal_sclk_dpm_enabled = 0; in ci_dpm_init()
5730 if ((rdev->pdev->device == 0x6658) && in ci_dpm_init()
5764 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; in ci_dpm_init()
5765 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; in ci_dpm_init()
5777 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; in ci_dpm_init()
5779 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; in ci_dpm_init()
5819 case 0: in ci_dpm_init()
5899 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || in ci_dpm_init()
5900 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) in ci_dpm_init()
5906 return 0; in ci_dpm_init()
5933 for (i = 0; i < ps->performance_level_count; i++) { in ci_dpm_print_power_state()
5961 return requested_state->performance_levels[0].sclk; in ci_dpm_get_sclk()
5972 return requested_state->performance_levels[0].mclk; in ci_dpm_get_mclk()