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/linux/drivers/memory/tegra/
H A Dtegra114.c15 .id = 0x00,
20 .reg = 0x34c,
21 .shift = 0,
22 .mask = 0xff,
23 .def = 0x0,
27 .id = 0x01,
32 .reg = 0x228,
36 .reg = 0x2e8,
37 .shift = 0,
38 .mask = 0xff,
[all …]
H A Dtegra30.c37 .id = 0x00,
42 .reg = 0x34c,
43 .shift = 0,
44 .mask = 0xff,
45 .def = 0x0,
50 .id = 0x01,
55 .reg = 0x228,
59 .reg = 0x2e8,
60 .shift = 0,
61 .mask = 0xff,
[all …]
H A Dtegra124.c16 .id = 0x00,
21 .reg = 0x34c,
22 .shift = 0,
23 .mask = 0xff,
24 .def = 0x0,
28 .id = 0x01,
33 .reg = 0x228,
37 .reg = 0x2e8,
38 .shift = 0,
39 .mask = 0xff,
[all …]
H A Dtegra210.c12 .id = 0x00,
16 .id = 0x01,
21 .reg = 0x228,
25 .reg = 0x2e8,
26 .shift = 0,
27 .mask = 0xff,
28 .def = 0x1e,
32 .id = 0x02,
37 .reg = 0x228,
41 .reg = 0x2f4,
[all …]
/linux/drivers/clk/sunxi-ng/
H A Dccu-sun20i-d1-r.c26 r_ahb_apb0_parents, 0x000,
27 0, 5, /* M */
30 0);
34 r_ahb_apb0_parents, 0x00c,
35 0, 5, /* M */
38 0);
42 0x11c, BIT(0), 0);
44 0x12c, BIT(0), 0);
46 0x1ac, BIT(0), 0);
53 r_ir_rx_parents, 0x1c0,
[all …]
/linux/drivers/media/platform/mediatek/mdp3/
H A Dmdp_reg_rsz.h10 #define PRZ_ENABLE 0x000
11 #define PRZ_CONTROL_1 0x004
12 #define PRZ_CONTROL_2 0x008
13 #define PRZ_INPUT_IMAGE 0x010
14 #define PRZ_OUTPUT_IMAGE 0x014
15 #define PRZ_HORIZONTAL_COEFF_STEP 0x018
16 #define PRZ_VERTICAL_COEFF_STEP 0x01c
17 #define PRZ_LUMA_HORIZONTAL_INTEGER_OFFSET 0x020
18 #define PRZ_LUMA_HORIZONTAL_SUBPIXEL_OFFSET 0x024
19 #define PRZ_LUMA_VERTICAL_INTEGER_OFFSET 0x028
[all …]
/linux/arch/arm/mach-footbridge/
H A Dnetwinder-hw.c28 #define IRDA_IO_BASE 0x180
29 #define GP1_IO_BASE 0x338
30 #define GP2_IO_BASE 0x33a
37 outb(0x87, 0x370); in wb977_open()
38 outb(0x87, 0x370); in wb977_open()
43 outb(0xaa, 0x370); in wb977_close()
48 outb(reg, 0x370); in wb977_wb()
49 outb(val, 0x371); in wb977_wb()
54 outb(reg, 0x370); in wb977_ww()
55 outb(val >> 8, 0x371); in wb977_ww()
[all …]
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-qserdes-txrx-v6_20.h9 #define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
10 #define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
11 #define QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN 0xac
12 #define QSERDES_V6_20_TX_LANE_MODE_1 0x78
13 #define QSERDES_V6_20_TX_LANE_MODE_2 0x7c
14 #define QSERDES_V6_20_TX_LANE_MODE_3 0x80
16 #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2 0x08
17 #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3 0x0c
18 #define QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2 0x18
19 #define QSERDES_V6_20_RX_UCDR_PI_CONTROLS 0x20
[all …]
H A Dphy-qcom-qmp-pcie-qhp.h10 #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14
11 #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20
12 #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24
13 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28
14 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c
15 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34
16 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38
17 #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54
18 #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58
19 #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c
[all …]
/linux/Documentation/devicetree/bindings/nvmem/
H A Dst,stm32-romem.yaml34 "^.*@[0-9a-f]+$":
59 reg = <0x1fff7800 0x400>;
64 reg = <0x22c 0x2>;
68 reg = <0xe4 0x8>;
/linux/drivers/net/ethernet/sunplus/
H A Dspl2sw_register.h10 #define L2SW_SW_INT_STATUS_0 0x0
11 #define L2SW_SW_INT_MASK_0 0x4
12 #define L2SW_FL_CNTL_TH 0x8
13 #define L2SW_CPU_FL_CNTL_TH 0xc
14 #define L2SW_PRI_FL_CNTL 0x10
15 #define L2SW_VLAN_PRI_TH 0x14
16 #define L2SW_EN_TOS_BUS 0x18
17 #define L2SW_TOS_MAP0 0x1c
18 #define L2SW_TOS_MAP1 0x20
19 #define L2SW_TOS_MAP2 0x24
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7925/
H A Dregs.h9 #define MT_MDP_BASE 0x820cc800
12 #define MT_MDP_DCR0 MT_MDP(0x000)
16 #define MT_MDP_DCR1 MT_MDP(0x004)
19 #define MT_MDP_BNRCFR0(_band) MT_MDP(0x090 + ((_band) << 8))
24 #define MT_MDP_BNRCFR1(_band) MT_MDP(0x094 + ((_band) << 8))
28 #define MT_MDP_TO_HIF 0
31 #define MT_WFDMA0_HOST_INT_ENA MT_WFDMA0(0x228)
32 #define MT_WFDMA0_HOST_INT_DIS MT_WFDMA0(0x22c)
65 #define MT_RX_DATA_RING_BASE MT_WFDMA0(0x500)
67 #define MT_INFRA_CFG_BASE 0xd1000
[all …]
/linux/include/linux/bcma/
H A Dbcma_driver_gmac_cmn.h7 #define BCMA_GMAC_CMN_STAG0 0x000
8 #define BCMA_GMAC_CMN_STAG1 0x004
9 #define BCMA_GMAC_CMN_STAG2 0x008
10 #define BCMA_GMAC_CMN_STAG3 0x00C
11 #define BCMA_GMAC_CMN_PARSER_CTL 0x020
12 #define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
13 #define BCMA_GMAC_CMN_PHY_ACCESS 0x100
14 #define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
15 #define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
17 #define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000
[all …]
/linux/sound/soc/fsl/
H A Dfsl_audmix.h15 #define FSL_AUDMIX_CTR 0x200 /* Control */
16 #define FSL_AUDMIX_STR 0x204 /* Status */
18 #define FSL_AUDMIX_ATCR0 0x208 /* Attenuation Control */
19 #define FSL_AUDMIX_ATIVAL0 0x20c /* Attenuation Initial Value */
20 #define FSL_AUDMIX_ATSTPUP0 0x210 /* Attenuation step up factor */
21 #define FSL_AUDMIX_ATSTPDN0 0x214 /* Attenuation step down factor */
22 #define FSL_AUDMIX_ATSTPTGT0 0x218 /* Attenuation step target */
23 #define FSL_AUDMIX_ATTNVAL0 0x21c /* Attenuation Value */
24 #define FSL_AUDMIX_ATSTP0 0x220 /* Attenuation step number */
26 #define FSL_AUDMIX_ATCR1 0x228 /* Attenuation Control */
[all …]
/linux/drivers/devfreq/event/
H A Dexynos-ppmu.h13 PPMU_DISABLE = 0,
18 PPMU_PMNCNT0 = 0,
30 PPMU_RO_BUSY_CYCLE_CNT = 0x0,
31 PPMU_WO_BUSY_CYCLE_CNT = 0x1,
32 PPMU_RW_BUSY_CYCLE_CNT = 0x2,
33 PPMU_RO_REQUEST_CNT = 0x3,
34 PPMU_WO_REQUEST_CNT = 0x4,
35 PPMU_RO_DATA_CNT = 0x5,
36 PPMU_WO_DATA_CNT = 0x6,
37 PPMU_RO_LATENCY = 0x12,
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
H A Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
H A Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
/linux/drivers/gpu/drm/bridge/
H A Dnwl-dsi.h12 #define NWL_DSI_CFG_NUM_LANES 0x0
13 #define NWL_DSI_CFG_NONCONTINUOUS_CLK 0x4
14 #define NWL_DSI_CFG_T_PRE 0x8
15 #define NWL_DSI_CFG_T_POST 0xc
16 #define NWL_DSI_CFG_TX_GAP 0x10
17 #define NWL_DSI_CFG_AUTOINSERT_EOTP 0x14
18 #define NWL_DSI_CFG_EXTRA_CMDS_AFTER_EOTP 0x18
19 #define NWL_DSI_CFG_HTX_TO_COUNT 0x1c
20 #define NWL_DSI_CFG_LRX_H_TO_COUNT 0x20
21 #define NWL_DSI_CFG_BTA_H_TO_COUNT 0x24
[all …]
/linux/drivers/net/ethernet/mediatek/
H A Dmtk_ppe_regs.h7 #define MTK_PPE_GLO_CFG 0x200
8 #define MTK_PPE_GLO_CFG_EN BIT(0)
23 #define MTK_PPE_FLOW_CFG 0x204
42 #define MTK_PPE_IP_PROTO_CHK 0x208
43 #define MTK_PPE_IP_PROTO_CHK_IPV4 GENMASK(15, 0)
46 #define MTK_PPE_TB_CFG 0x21c
47 #define MTK_PPE_TB_CFG_ENTRY_NUM GENMASK(2, 0)
63 #define MTK_PPE_BIND_LMT1 0x230
66 #define MTK_PPE_KEEPALIVE 0x234
86 #define MTK_PPE_TB_BASE 0x220
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mt6735-apmixedsys.c14 #define AP_PLL_CON_5 0x014
15 #define ARMPLL_CON0 0x200
16 #define ARMPLL_CON1 0x204
17 #define ARMPLL_PWR_CON0 0x20c
18 #define MAINPLL_CON0 0x210
19 #define MAINPLL_CON1 0x214
20 #define MAINPLL_PWR_CON0 0x21c
21 #define UNIVPLL_CON0 0x220
22 #define UNIVPLL_CON1 0x224
23 #define UNIVPLL_PWR_CON0 0x22c
[all …]
/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_lvds_regs.h13 #define LVDCR0 0x0000
16 #define LVDCR0_LVMD_MASK (0xf << 8)
22 #define LVDCR0_LVRES (1 << 0)
24 #define LVDCR1 0x0004
27 #define LVDCR1_CLKSTBY (3 << 0)
29 #define LVDPLLCR 0x0008
34 #define LVDPLLCR_PLLDLYCNT_150M (0x1bf << 0)
35 #define LVDPLLCR_PLLDLYCNT_121M (0x22c << 0)
36 #define LVDPLLCR_PLLDLYCNT_60M (0x77b << 0)
37 #define LVDPLLCR_PLLDLYCNT_38M (0x69a << 0)
[all …]
/linux/drivers/media/pci/tw68/
H A Dtw68-reg.h23 #define TW68_DMAC 0x000
24 #define TW68_DMAP_SA 0x004
25 #define TW68_DMAP_EXE 0x008
26 #define TW68_DMAP_PP 0x00c
27 #define TW68_VBIC 0x010
28 #define TW68_SBUSC 0x014
29 #define TW68_SBUSSD 0x018
30 #define TW68_INTSTAT 0x01C
31 #define TW68_INTMASK 0x020
32 #define TW68_GPIOC 0x024
[all …]

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