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12

/freebsd/lib/msun/src/
H A De_hypotf.c26 ha &= 0x7fffffff; in hypotf()
28 hb &= 0x7fffffff; in hypotf()
32 if((ha-hb)>0xf000000) {return a+b;} /* x/y > 2**30 */ in hypotf()
33 k=0; in hypotf()
34 if(ha > 0x58800000) { /* a>2**50 */ in hypotf()
35 if(ha >= 0x7f800000) { /* Inf or NaN */ in hypotf()
37 w = fabsl(x+0.0L)-fabsf(y+0); in hypotf()
38 if(ha == 0x7f800000) w = a; in hypotf()
39 if(hb == 0x7f800000) w = b; in hypotf()
43 ha -= 0x22000000; hb -= 0x22000000; k += 68; in hypotf()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/ufs/
H A Dsprd,ums9620-ufs.yaml67 reg = <0x22000000 0x3000>;
/freebsd/contrib/arm-optimized-routines/math/aarch64/advsimd/
H A Dsinf.c19 .poly = { V4 (-0x1.555548p-3f), V4 (0x1.110df4p-7f), V4 (-0x1.9f42eap-13f),
20 V4 (0x1.5b2e76p-19f) },
22 .pi_1 = V4 (0x1.921fb6p+1f),
23 .pi_2 = V4 (-0x1.777a5cp-24f),
24 .pi_3 = V4 (-0x1.ee59dap-49f),
26 .inv_pi = V4 (0x1.45f306p-2f),
27 .range_val = V4 (0x1p20f)
31 /* asuint32(0x1p-59f), below which multiply by inv_pi underflows. */
32 # define TinyBound v_u32 (0x22000000)
34 # define Thresh v_u32 (0x27800000)
[all …]
/freebsd/sys/dev/mpt/mpilib/
H A Dmpi_log_fc.h47 * The value is 0xabcccccc where
51 * 0 = FCP Initiator
67 MPI_IOCLOGINFO_FC_INIT_BASE = 0x20000000,
68 …MPI_IOCLOGINFO_FC_INIT_ERROR_OUT_OF_ORDER_FRAME = 0x20000001, /* received an out of order frame - …
69 …MPI_IOCLOGINFO_FC_INIT_ERROR_BAD_START_OF_FRAME = 0x20000002, /* Bad Rx Frame, bad start of frame …
70 …MPI_IOCLOGINFO_FC_INIT_ERROR_BAD_END_OF_FRAME = 0x20000003, /* Bad Rx Frame, bad end of frame pr…
71 MPI_IOCLOGINFO_FC_INIT_ERROR_OVER_RUN = 0x20000004, /* Bad Rx Frame, overrun */
72 …MPI_IOCLOGINFO_FC_INIT_ERROR_RX_OTHER = 0x20000005, /* Other errors caught by IOC which …
73 …MPI_IOCLOGINFO_FC_INIT_ERROR_SUBPROC_DEAD = 0x20000006, /* Main processor could not initiali…
74 MPI_IOCLOGINFO_FC_INIT_ERROR_RX_OVERRUN = 0x20000007, /* Scatter Gather overrun */
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dp1022ds.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x8000000>;
44 partition@0 {
45 reg = <0x0 0x03000000>;
51 reg = <0x03000000 0x00e00000>;
57 reg = <0x03e00000 0x00200000>;
63 reg = <0x04000000 0x00400000>;
69 reg = <0x04400000 0x03b00000>;
74 reg = <0x07f00000 0x00080000>;
80 reg = <0x07f80000 0x00080000>;
[all …]
/freebsd/sys/gnu/dev/bwn/phy_n/
H A Dif_bwn_phy_n_tables.c84 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
85 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
86 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
87 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
88 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
89 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
90 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
91 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
92 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
93 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
[all …]
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dspear13xx.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
36 reg = < 0xec801000 0x1000 >,
37 < 0xec800100 0x0100 >;
42 interrupts = <0 6 0x04>,
43 <0
[all...]
/freebsd/sys/contrib/device-tree/src/arm/ti/davinci/
H A Dda850.dtsi16 reg = <0xc0000000 0x0>;
21 #size-cells = <0>;
23 cpu: cpu@0 {
26 reg = <0>;
78 reg = <0xfffee000 0x2000>;
84 #clock-cells = <0>;
89 #clock-cells = <0>;
95 #clock-cells = <0>;
102 reg = <0x11800000 0x40000>,
103 <0x11e00000 0x8000>,
[all …]
/freebsd/sys/dts/powerpc/
H A Dp2041rdb.dts59 reg = <0x00000000 0x00000000 0x00000000 0x80000000>;
63 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
67 bman-portal@0 {
92 buffer-pool@0 {
94 fsl,bpid = <0>;
95 fsl,bpool-cfg = <0 0x100 0 1 0 0x100>;
100 qportal0: qman-portal@0 {
187 flash@0 {
191 reg = <0>;
195 reg = <0x00000000 0x00100000>;
[all …]
H A Dp3041ds.dts60 reg = <0x00000000 0x00000000 0x00000000 0x80000000>;
64 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
68 bman-portal@0 {
93 buffer-pool@0 {
95 fsl,bpid = <0>;
96 fsl,bpool-cfg = <0 0x100 0 1 0 0x100>;
101 qportal0: qman-portal@0 {
188 flash@0 {
192 reg = <0>;
196 reg = <0x00000000 0x00100000>;
[all …]
H A Dp5020ds.dts60 reg = <0x00000000 0x00000000 0x00000000 0x80000000>;
64 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
68 bman-portal@0 {
91 buffer-pool@0 {
93 fsl,bpid = <0>;
94 fsl,bpool-cfg = <0 0x100 0 1 0 0x100>;
99 qportal0: qman-portal@0 {
184 flash@0 {
188 reg = <0>;
192 reg = <0x00000000 0x00100000>;
[all …]
H A Dp3041si.dtsi103 #size-cells = <0>;
105 cpu0: PowerPC,e500mc@0 {
107 reg = <0>;
145 dcsr-epu@0 {
147 interrupts = <52 2 0 0
148 84 2 0 0
149 85 2 0 0>;
151 reg = <0x0 0x1000>;
155 reg = <0x1000 0x1000 0x1000000 0x8000>;
159 reg = <0x2000 0x1000>;
[all …]
H A Dp2041si.dtsi102 #size-cells = <0>;
104 cpu0: PowerPC,e500mc@0 {
106 reg = <0>;
144 dcsr-epu@0 {
146 interrupts = <52 2 0 0
147 84 2 0 0
148 85 2 0 0>;
150 reg = <0x0 0x1000>;
154 reg = <0x1000 0x1000 0x1000000 0x8000>;
158 reg = <0x2000 0x1000>;
[all …]
H A Dp5020si.dtsi109 #size-cells = <0>;
111 cpu0: PowerPC,e5500@0 {
113 reg = <0>;
135 dcsr-epu@0 {
137 interrupts = <52 2 0 0
138 84 2 0 0
139 85 2 0 0>;
141 reg = <0x0 0x1000>;
145 reg = <0x1000 0x1000 0x1000000 0x8000>;
149 reg = <0x2000 0x1000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhi6220-hikey.dts32 * 0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using
33 * 0x05f0,1000 - 0x05f0,1fff: Reboot reason
34 * 0x06df,f000 - 0x06df,ffff: Mailbox message data
35 * 0x0740,f000 - 0x0740,ffff: MCU firmware section
36 * 0x21f0,0000 - 0x21ff,ffff: pstore/ramoops buffer
37 * 0x3e00,0000 - 0x3fff,ffff: OP-TEE
39 memory@0 {
41 reg = <0x00000000 0x00000000 0x00000000 0x05e00000>,
42 <0x00000000 0x05f00000 0x00000000 0x00001000>,
43 <0x00000000 0x05f02000 0x00000000 0x00efd000>,
[all …]
/freebsd/sys/contrib/xen/
H A Darch-arm.h170 #define XEN_HYPERCALL_TAG 0XEA1
199 _sxghr_tmp->q = 0; \
201 } while ( 0 )
294 #define _VGCF_online 0
310 #define XEN_DOMCTL_CONFIG_GIC_NATIVE 0
314 #define XEN_DOMCTL_CONFIG_TEE_NONE 0
333 * = 0 => property not present
334 * > 0 => Value of the property
362 #define PSR_IT_MASK (0x0600fc00) /* Thumb If-Then Mask */
366 #define PSR_MODE_USR 0x10
[all …]
/freebsd/sys/contrib/openzfs/module/icp/asm-x86_64/aes/
H A Daestab2.h49 0x00000001, 0x00000002, 0x00000004, 0x00000008,
50 0x00000010, 0x00000020, 0x00000040, 0x00000080,
51 0x0000001b, 0x00000036
57 0x00000063, 0x0000007c, 0x00000077, 0x0000007b,
58 0x000000f2, 0x0000006b, 0x0000006f, 0x000000c5,
59 0x00000030, 0x00000001, 0x00000067, 0x0000002b,
60 0x000000fe, 0x000000d7, 0x000000ab, 0x00000076,
61 0x000000ca, 0x00000082, 0x000000c9, 0x0000007d,
62 0x000000fa, 0x00000059, 0x00000047, 0x000000f0,
63 0x000000ad, 0x000000d4, 0x000000a2, 0x000000af,
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_init_values.h35 0x00030003, 0xffff0000, /* if phase != 'engine', skip 3 ops (no DMAE) */
36 0x00020002, 0x00020000, /* if mode != '!asic', skip 2 ops */
37 0x0280c201, 0x00000000, /* write 0x0 to address 0x50184 */
38 0x02810201, 0x00000000, /* write 0x0 to address 0x50204 */
40 0x00110003, 0xffff0000, /* if phase != 'engine', skip 17 ops (no DMAE) */
41 0x00030002, 0x00020000, /* if mode != '!asic', skip 3 ops */
42 0x0048c201, 0x00000000, /* write 0x0 to address 0x9184 */
43 0x0048d201, 0x00000000, /* write 0x0 to address 0x91a4 */
44 0x004ba601, 0x00000001, /* write 0x1 to address 0x974c */
45 0x00020002, 0x00be0000, /* if mode != '(!asic)&bb', skip 2 ops */
[all …]
H A Dmcp_public.h51 #define OFFSIZE_OFFSET_OFFSET 0
52 #define OFFSIZE_OFFSET_MASK 0x0000ffff
55 #define OFFSIZE_SIZE_MASK 0xffff0000
70 u32 speed; /* 0 = autoneg, 1000/10000/20000/25000/40000/50000/100000 */
71 #define ETH_SPEED_AUTONEG 0
72 #define ETH_SPEED_SMARTLINQ 0x8 /* deprecated - use link_modes field instead */
75 #define ETH_PAUSE_NONE 0x0
76 #define ETH_PAUSE_AUTONEG 0x1
77 #define ETH_PAUSE_RX 0x2
78 #define ETH_PAUSE_TX 0x4
[all …]
/freebsd/tests/sys/cddl/zfs/tests/txg_integrity/
H A Dtxg_integrity.c84 #define USE_MMAP 0
90 //partitions[-1] is understood to be 0 and partitions[NUM_CHUNKS] must be 1.0
94 //8 / (NUM_CHUNKS * CLUSTERSIZE) = 1 / 524288 = 0x0.00002
98 //chunk 0 corresponds to bit 1, chunk 1 to bit 2, etc
106 if (chunk == 0){ in get_chunk_range()
107 *begin = 0; in get_chunk_range()
117 leader_syncs = 0,
125 {0x2000000, 0x4000000, 0x6000000, 0x8000000, 0xa000000, 0xc000000, 0xe000000, 0x10000000,
126 0x12000000, 0x14000000, 0x16000000, 0x18000000, 0x1a000000, 0x1c000000, 0x1e000000, 0x20000000,
127 0x22000000, 0x24000000, 0x26000000, 0x28000000, 0x2a000000, 0x2c000000, 0x2e000000, 0x30000000,
[all …]
H A Dfsync_integrity.c61 * Every even-numbered thread, starting with the first (0th), will fsync()
98 //partitions[-1] is understood to be 0 and partitions[NUM_CHUNKS] must be 1.0
102 //8 / (NUM_CHUNKS * CLUSTERSIZE) = 1 / 524288 = 0x0.00002
116 if (chunk == 0){ in get_chunk_range()
117 *begin = 0; in get_chunk_range()
129 {0x2000000, 0x4000000, 0x6000000, 0x8000000, 0xa000000, 0xc000000, 0xe000000, 0x10000000,
130 0x12000000, 0x14000000, 0x16000000, 0x18000000, 0x1a000000, 0x1c000000, 0x1e000000, 0x20000000,
131 0x22000000, 0x24000000, 0x26000000, 0x28000000, 0x2a000000, 0x2c000000, 0x2e000000, 0x30000000,
132 0x32000000, 0x34000000, 0x36000000, 0x38000000, 0x3a000000, 0x3c000000, 0x3e000000, 0x40000000,
133 0x42000000, 0x44000000, 0x46000000, 0x48000000, 0x4a000000, 0x4c000000, 0x4e000000, 0x50000000,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepMask.h3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
17 0xf0000000,
18 0xb0000000,
19 0x0fe03fe0,
20 0 },
23 0xffc00000,
24 0x76000000,
25 0x00203fe0,
26 0 },
29 0xff800000,
[all …]
/freebsd/sys/dev/msk/
H A Dif_mskreg.h102 #define VENDORID_SK 0x1148
107 #define VENDORID_MARVELL 0x11AB
112 #define VENDORID_DLINK 0x1186
117 #define DEVICEID_SK_YUKON2 0x9000
118 #define DEVICEID_SK_YUKON2_EXPR 0x9e00
123 #define DEVICEID_MRVL_8021CU 0x4340
124 #define DEVICEID_MRVL_8022CU 0x4341
125 #define DEVICEID_MRVL_8061CU 0x4342
126 #define DEVICEID_MRVL_8062CU 0x4343
127 #define DEVICEID_MRVL_8021X 0x4344
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.td3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
18 def SDT_CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>,
20 def SDT_CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
24 def SDT_LoongArchCall : SDTypeProfile<0, -1, [SDTCisVT<0, GRLenVT>]>;
26 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVT<0, i64>
30 SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3>,
35 SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisInt<2>, SDTCisSameAs<2, 3>
39 def SDT_LoongArchVI : SDTypeProfile<0, 1, [SDTCisVT<0, GRLenVT>]>;
41 def SDT_LoongArchCsrrd : SDTypeProfile<1, 1, [SDTCisInt<0>,
43 def SDT_LoongArchCsrwr : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsc8280xp.dtsi33 #clock-cells = <0>;
38 #clock-cells = <0>;
45 #size-cells = <0>;
47 CPU0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
58 qcom,freq-domain = <&cpufreq_hw 0>;
78 reg = <0x0 0x100>;
79 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]

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