1 /*
2 * Single-precision vector sin function.
3 *
4 * Copyright (c) 2019-2024, Arm Limited.
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
6 */
7
8 #include "mathlib.h"
9 #include "v_math.h"
10 #include "test_defs.h"
11 #include "test_sig.h"
12
13 static const struct data
14 {
15 float32x4_t poly[4];
16 float32x4_t range_val, inv_pi, pi_1, pi_2, pi_3;
17 } data = {
18 /* 1.886 ulp error. */
19 .poly = { V4 (-0x1.555548p-3f), V4 (0x1.110df4p-7f), V4 (-0x1.9f42eap-13f),
20 V4 (0x1.5b2e76p-19f) },
21
22 .pi_1 = V4 (0x1.921fb6p+1f),
23 .pi_2 = V4 (-0x1.777a5cp-24f),
24 .pi_3 = V4 (-0x1.ee59dap-49f),
25
26 .inv_pi = V4 (0x1.45f306p-2f),
27 .range_val = V4 (0x1p20f)
28 };
29
30 #if WANT_SIMD_EXCEPT
31 /* asuint32(0x1p-59f), below which multiply by inv_pi underflows. */
32 # define TinyBound v_u32 (0x22000000)
33 /* RangeVal - TinyBound. */
34 # define Thresh v_u32 (0x27800000)
35 #endif
36
37 #define C(i) d->poly[i]
38
39 static float32x4_t VPCS_ATTR NOINLINE
special_case(float32x4_t x,float32x4_t y,uint32x4_t odd,uint32x4_t cmp)40 special_case (float32x4_t x, float32x4_t y, uint32x4_t odd, uint32x4_t cmp)
41 {
42 /* Fall back to scalar code. */
43 y = vreinterpretq_f32_u32 (veorq_u32 (vreinterpretq_u32_f32 (y), odd));
44 return v_call_f32 (sinf, x, y, cmp);
45 }
46
V_NAME_F1(sin)47 float32x4_t VPCS_ATTR NOINLINE V_NAME_F1 (sin) (float32x4_t x)
48 {
49 const struct data *d = ptr_barrier (&data);
50 float32x4_t n, r, r2, y;
51 uint32x4_t odd, cmp;
52
53 #if WANT_SIMD_EXCEPT
54 uint32x4_t ir = vreinterpretq_u32_f32 (vabsq_f32 (x));
55 cmp = vcgeq_u32 (vsubq_u32 (ir, TinyBound), Thresh);
56 /* If fenv exceptions are to be triggered correctly, set any special lanes
57 to 1 (which is neutral w.r.t. fenv). These lanes will be fixed by
58 special-case handler later. */
59 r = vreinterpretq_f32_u32 (vbicq_u32 (vreinterpretq_u32_f32 (x), cmp));
60 #else
61 r = x;
62 cmp = vcageq_f32 (x, d->range_val);
63 #endif
64
65 /* n = rint(|x|/pi). */
66 n = vrndaq_f32 (vmulq_f32 (r, d->inv_pi));
67 odd = vshlq_n_u32 (vreinterpretq_u32_s32 (vcvtq_s32_f32 (n)), 31);
68
69 /* r = |x| - n*pi (range reduction into -pi/2 .. pi/2). */
70 r = vfmsq_f32 (r, d->pi_1, n);
71 r = vfmsq_f32 (r, d->pi_2, n);
72 r = vfmsq_f32 (r, d->pi_3, n);
73
74 /* y = sin(r). */
75 r2 = vmulq_f32 (r, r);
76 y = vfmaq_f32 (C (2), C (3), r2);
77 y = vfmaq_f32 (C (1), y, r2);
78 y = vfmaq_f32 (C (0), y, r2);
79 y = vfmaq_f32 (r, vmulq_f32 (y, r2), r);
80
81 if (unlikely (v_any_u32 (cmp)))
82 return special_case (x, y, odd, cmp);
83 return vreinterpretq_f32_u32 (veorq_u32 (vreinterpretq_u32_f32 (y), odd));
84 }
85
86 HALF_WIDTH_ALIAS_F1 (sin)
87
88 TEST_SIG (V, F, 1, sin, -3.1, 3.1)
89 TEST_ULP (V_NAME_F1 (sin), 1.4)
90 TEST_DISABLE_FENV_IF_NOT (V_NAME_F1 (sin), WANT_SIMD_EXCEPT)
91 TEST_SYM_INTERVAL (V_NAME_F1 (sin), 0, 0x1p20, 500000)
92 TEST_SYM_INTERVAL (V_NAME_F1 (sin), 0x1p20, inf, 10000)
93