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/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-usb2-mph-0.dtsi2 * QorIQ USB Host device tree stub [ controller @ offset 0x210000 ]
37 reg = <0x210000 0x1000>;
39 #size-cells = <0>;
40 interrupts = <44 0x2 0 0>;
H A Dqonverge-usb2-dr-0.dtsi2 * QorIQ Qonverge USB Host device tree stub [ controller @ offset 0x210000 ]
37 reg = <0x210000 0x1000>;
39 #size-cells = <0>;
40 interrupts = <44 0x2 0 0>;
/linux/drivers/rtc/
H A Drtc-gamecube.c12 * This device sits on a bus named EXI (which is similar to SPI), channel 0,
40 #define EXICSR 0
45 #define EXICSR_DEV 0x380
46 #define EXICSR_DEV1 0x100
47 #define EXICSR_CLK 0x070
48 #define EXICSR_CLK_1MHZ 0x000
49 #define EXICSR_CLK_2MHZ 0x010
50 #define EXICSR_CLK_4MHZ 0x020
51 #define EXICSR_CLK_8MHZ 0x030
52 #define EXICSR_CLK_16MHZ 0x040
[all …]
/linux/Documentation/devicetree/bindings/dma/
H A Dnvidia,tegra186-gpc-dma.yaml79 reg = <0x2600000 0x210000>;
116 dma-channel-mask = <0xfffffffe>;
/linux/drivers/media/pci/intel/ipu6/
H A Dipu6-platform-regs.h11 * locates in one single space starts from 0 but in different sctions with
12 * different addresses, the subsystem offsets are defined to 0 as the
13 * register definition will have the address offset to 0.
15 #define IPU6_UNIFIED_OFFSET 0
17 #define IPU6_ISYS_IOMMU0_OFFSET 0x2e0000
18 #define IPU6_ISYS_IOMMU1_OFFSET 0x2e0500
19 #define IPU6_ISYS_IOMMUI_OFFSET 0x2e0a00
21 #define IPU6_PSYS_IOMMU0_OFFSET 0x1b0000
22 #define IPU6_PSYS_IOMMU1_OFFSET 0x1b0700
23 #define IPU6_PSYS_IOMMU1R_OFFSET 0x1b0e00
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-3720-db.dts27 memory@0 {
29 reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
55 gpios-states = <0>;
56 states = <1800000 0x1
57 3300000 0x0>;
72 /* Gigabit module on CON19(V2.0)/CON21(V1.4) */
75 pinctrl-0 = <&rgmii_pins>;
81 /* Gigabit module on CON18(V2.0)/CON20(V1.4) */
90 pinctrl-0 = <&i2c1_pins>;
98 reg = <0x22>;
[all …]
H A Darmada-ap80x.dtsi41 reg = <0x0 0x4000000 0x0 0x200000>;
46 reg = <0 0x4400000 0 0x1000000>;
77 ranges = <0x0 0x0 0xf0000000 0x1000000>;
81 reg = <0x100000 0x100000>;
105 reg = <0x210000 0x10000>,
106 <0x220000 0x20000>,
107 <0x240000 0x20000>,
108 <0x260000 0x20000>;
113 reg = <0x280000 0x1000>;
120 reg = <0x290000 0x1000>;
[all …]
/linux/drivers/net/ethernet/cavium/thunder/
H A Dnic_reg.h13 #define NIC_PF_CFG (0x0000)
14 #define NIC_PF_STATUS (0x0010)
15 #define NIC_PF_INTR_TIMER_CFG (0x0030)
16 #define NIC_PF_BIST_STATUS (0x0040)
17 #define NIC_PF_SOFT_RESET (0x0050)
18 #define NIC_PF_TCP_TIMER (0x0060)
19 #define NIC_PF_BP_CFG (0x0080)
20 #define NIC_PF_RRM_CFG (0x0088)
21 #define NIC_PF_CQM_CFG (0x00A0)
22 #define NIC_PF_CNM_CF (0x00A8)
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a-kontron-sl28.dts85 reg = <0x5>;
95 nvmem-cells = <&base_mac_address 0>;
118 flash@0 {
122 reg = <0>;
132 partition@0 {
133 reg = <0x000000 0x010000>;
139 reg = <0x010000 0x1d0000>;
145 reg = <0x200000 0x010000>;
150 reg = <0x210000 0x1d0000>;
155 reg = <0x3e0000 0x020000>;
[all …]
H A Dimx8ulp.dtsi37 #size-cells = <0>;
39 A35_0: cpu@0 {
42 reg = <0x0 0x0>;
51 reg = <0x0 0x1>;
68 arm,psci-suspend-param = <0x0>;
79 reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */
80 <0x0 0x2d440000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
103 thermal-sensors = <&scmi_sensor 0>;
133 #clock-cells = <0>;
140 #clock-cells = <0>;
[all …]
H A Dimx95.dtsi24 #size-cells = <0>;
31 arm,psci-suspend-param = <0x0010033>;
40 A55_0: cpu@0 {
43 reg = <0x0>;
61 reg = <0x100>;
79 reg = <0x200>;
97 reg = <0x300>;
115 reg = <0x400>;
133 reg = <0x500>;
248 #clock-cells = <0>;
[all …]
/linux/arch/arm64/boot/dts/arm/
H A Drtsm_ve-motherboard.dtsi13 #clock-cells = <0>;
20 #clock-cells = <0>;
27 #clock-cells = <0>;
49 #clock-cells = <0>;
55 arm,vexpress-sysreg,func = <5 0>;
60 arm,vexpress-sysreg,func = <7 0>;
65 arm,vexpress-sysreg,func = <8 0>;
70 arm,vexpress-sysreg,func = <9 0>;
75 arm,vexpress-sysreg,func = <11 0>;
83 ranges = <0 0x8000000 0 0x8000000 0x18000000>;
[all …]
/linux/arch/mips/include/asm/sn/sn0/
H A Dhubmd.h29 #define MD_BASE 0x200000
30 #define MD_BASE_PERF 0x210000
31 #define MD_BASE_JUNK 0x220000
33 #define MD_IO_PROTECT 0x200000 /* MD and core register protection */
34 #define MD_IO_PROT_OVRRD 0x200008 /* Clear my bit in MD_IO_PROTECT */
35 #define MD_HSPEC_PROTECT 0x200010 /* BDDIR, LBOOT, RBOOT protection */
36 #define MD_MEMORY_CONFIG 0x200018 /* Memory/Directory DIMM control */
37 #define MD_REFRESH_CONTROL 0x200020 /* Memory/Directory refresh ctrl */
38 #define MD_FANDOP_CAC_STAT 0x200028 /* Fetch-and-op cache status */
39 #define MD_MIG_DIFF_THRESH 0x200030 /* Page migr. count diff thresh. */
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dsama5d2.dtsi29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
35 d-cache-size = <0x8000>; // L1, 32 KB
36 i-cache-size = <0x8000>; // L1, 32 KB
43 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>;
48 reg = <0x740000 0x1000>;
64 reg = <0x73c000 0x1000>;
80 reg = <0x20000000 0x20000000>;
86 #clock-cells = <0>;
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588-h96-max-v58.dts53 pinctrl-0 = <&ir_receiver_pin>;
59 pinctrl-0 = <&led_pins>;
83 pinctrl-0 = <&pcie2_0_pow>;
95 pinctrl-0 = <&wl_en>;
118 pinctrl-0 = <&vcc5v0_host_en>;
130 pinctrl-0 = <&vcc5v0_otg_en>;
146 #sound-dai-cells = <0>;
234 pinctrl-0 = <&i2c0m2_xfer>;
239 reg = <0x42>;
256 reg = <0x43>;
[all …]
H A Drk3588-evb1-v10.dts64 pinctrl-0 = <&hp_detect>;
106 pinctrl-0 = <&headphone_amplifier_en>;
114 pinctrl-0 = <&speaker_amplifier_en>;
121 pwms = <&pwm2 0 25000 0>;
191 pinctrl-0 = <&typec5v_pwren>;
217 pinctrl-0 = <&vcc3v3_pcie30_en>;
235 pinctrl-0 = <&wifi_pwren>;
252 pinctrl-0 = <&vcc5v0_host_en>;
345 pinctrl-0 = <&gmac0_miim
351 rx_delay = <0x00>;
[all …]
/linux/tools/testing/selftests/kvm/arm64/
H A Dvgic_init.c56 TEST_ASSERT(val == want, "%s; want '0x%x', got '0x%x'", msg, want, val); in v3_redist_reg_get()
62 GUEST_SYNC(0); in guest_code()
71 return __vcpu_run(vcpu) ? -errno : 0; in run_vcpu()
113 .size = 0x10000,
114 .alignment = 0x10000,
119 .size = NR_VCPUS * 0x20000,
120 .alignment = 0x10000,
125 .size = 0x1000,
126 .alignment = 0x100
[all...]
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra186.dtsi20 reg = <0x0 0x00100000 0x0 0xf000>,
21 <0x0 0x0010f000 0x0 0x1000>;
27 reg = <0x0 0x2200000 0x0 0x10000>,
28 <0x0 0x2210000 0x0 0x10000>;
44 reg = <0x0 0x02490000 0x0 0x10000>;
71 snps,burst-map = <0x7>;
78 reg = <0x0 0x2600000 0x0 0x210000>;
116 dma-channel-mask = <0xfffffffe>;
129 ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>;
134 reg = <0x0 0x02900800 0x0 0x800>;
[all …]
H A Dtegra194.dtsi20 bus@0 {
25 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
29 reg = <0x0 0x00100000 0x0 0xf000>,
30 <0x0 0x0010f000 0x0 0x1000>;
36 reg = <0x0 0x2200000 0x0 0x10000>,
37 <0x0 0x2210000 0x0 0x10000>;
90 gpio-ranges = <&pinmux 0 0 169>;
95 reg = <0x0 0x02300000 0x0 0x1000>;
105 reg = <0x0 0x2390000 0x0 0x1000>,
106 <0x0 0x23a0000 0x0 0x1000>,
[all …]
H A Dtegra234.dtsi31 bus@0 {
36 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
40 reg = <0x0 0x00100000 0x0 0xf000>,
41 <0x0 0x0010f000 0x0 0x1000>;
47 reg = <0x0 0x02080000 0x0 0x00121000>;
48 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
70 reg = <0x0 0x02200000 0x0 0x10000>,
71 <0x0 0x02210000 0x0 0x10000>;
124 gpio-ranges = <&pinmux 0 0 164>;
129 reg = <0x0 0x2430000 0x0 0x19100>;
[all …]
/linux/arch/mips/cavium-octeon/
H A Docteon-irq.c58 #define CIU3_CONST 0x220
59 #define CIU3_IDT_CTL(_idt) ((_idt) * 8 + 0x110000)
60 #define CIU3_IDT_PP(_idt, _idx) ((_idt) * 32 + (_idx) * 8 + 0x120000)
61 #define CIU3_IDT_IO(_idt) ((_idt) * 8 + 0x130000)
62 #define CIU3_DEST_PP_INT(_pp_ip) ((_pp_ip) * 8 + 0x200000)
63 #define CIU3_DEST_IO_INT(_io) ((_io) * 8 + 0x210000)
64 #define CIU3_ISC_CTL(_intsn) ((_intsn) * 8 + 0x80000000)
65 #define CIU3_ISC_W1C(_intsn) ((_intsn) * 8 + 0x90000000)
66 #define CIU3_ISC_W1S(_intsn) ((_intsn) * 8 + 0xa0000000)
115 return 0; in octeon_irq_set_ciu_mapping()
[all …]
/linux/drivers/ptp/
H A Dptp_ocp.c28 #define PCI_VENDOR_ID_FACEBOOK 0x1d9b
29 #define PCI_DEVICE_ID_FACEBOOK_TIMECARD 0x0400
31 #define PCI_VENDOR_ID_CELESTICA 0x18d4
32 #define PCI_DEVICE_ID_CELESTICA_TIMECARD 0x1008
34 #define PCI_VENDOR_ID_OROLIA 0x1ad7
35 #define PCI_DEVICE_ID_OROLIA_ARTCARD 0xa000
37 #define PCI_VENDOR_ID_ADVA 0xad5a
38 #define PCI_DEVICE_ID_ADVA_TIMECARD 0x0400
76 #define OCP_CTRL_ENABLE BIT(0)
84 #define OCP_STATUS_IN_SYNC BIT(0)
[all …]