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/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Ddcore0_hmmu0_stlb_masks.h24 #define DCORE0_HMMU0_STLB_BUSY_BUSY_SHIFT 0
25 #define DCORE0_HMMU0_STLB_BUSY_BUSY_MASK 0xFFFFFFFF
28 #define DCORE0_HMMU0_STLB_ASID_ASID_SHIFT 0
29 #define DCORE0_HMMU0_STLB_ASID_ASID_MASK 0x3FF
32 #define DCORE0_HMMU0_STLB_HOP0_PA43_12_HOP0_PA43_12_SHIFT 0
33 #define DCORE0_HMMU0_STLB_HOP0_PA43_12_HOP0_PA43_12_MASK 0xFFFFFFFF
36 #define DCORE0_HMMU0_STLB_HOP0_PA63_44_HOP0_PA63_44_SHIFT 0
37 #define DCORE0_HMMU0_STLB_HOP0_PA63_44_HOP0_PA63_44_MASK 0xFFFFF
40 #define DCORE0_HMMU0_STLB_CACHE_INV_PRODUCER_INDEX_SHIFT 0
41 #define DCORE0_HMMU0_STLB_CACHE_INV_PRODUCER_INDEX_MASK 0xFF
[all …]
H A Dpmmu_hbw_stlb_masks.h24 #define PMMU_HBW_STLB_BUSY_BUSY_SHIFT 0
25 #define PMMU_HBW_STLB_BUSY_BUSY_MASK 0xFFFFFFFF
28 #define PMMU_HBW_STLB_ASID_ASID_SHIFT 0
29 #define PMMU_HBW_STLB_ASID_ASID_MASK 0x3FF
32 #define PMMU_HBW_STLB_HOP0_PA43_12_HOP0_PA43_12_SHIFT 0
33 #define PMMU_HBW_STLB_HOP0_PA43_12_HOP0_PA43_12_MASK 0xFFFFFFFF
36 #define PMMU_HBW_STLB_HOP0_PA63_44_HOP0_PA63_44_SHIFT 0
37 #define PMMU_HBW_STLB_HOP0_PA63_44_HOP0_PA63_44_MASK 0xFFFFF
40 #define PMMU_HBW_STLB_CACHE_INV_PRODUCER_INDEX_SHIFT 0
41 #define PMMU_HBW_STLB_CACHE_INV_PRODUCER_INDEX_MASK 0xFF
[all …]
/linux/drivers/media/platform/verisilicon/
H A Drockchip_vpu981_regs.h28 #define av1_dec_e AV1_DEC_REG(1, 0, 0x1)
29 #define av1_dec_abort_e AV1_DEC_REG(1, 5, 0x1)
30 #define av1_dec_tile_int_e AV1_DEC_REG(1, 7, 0x1)
32 #define av1_dec_clk_gate_e AV1_DEC_REG(2, 10, 0x1)
34 #define av1_dec_out_ec_bypass AV1_DEC_REG(3, 8, 0x1)
35 #define av1_write_mvs_e AV1_DEC_REG(3, 12, 0x1)
36 #define av1_filtering_dis AV1_DEC_REG(3, 14, 0x1)
37 #define av1_dec_out_dis AV1_DEC_REG(3, 15, 0x1)
38 #define av1_dec_out_ec_byte_word AV1_DEC_REG(3, 16, 0x1)
39 #define av1_skip_mode AV1_DEC_REG(3, 26, 0x1)
[all …]
H A Drockchip_vpu2_regs.h13 #define VEPU_REG_VP8_QUT_1ST(i) (0x000 + ((i) * 0x24))
14 #define VEPU_REG_VP8_QUT_DC_Y2(x) (((x) & 0x3fff) << 16)
15 #define VEPU_REG_VP8_QUT_DC_Y1(x) (((x) & 0x3fff) << 0)
16 #define VEPU_REG_VP8_QUT_2ND(i) (0x004 + ((i) * 0x24))
17 #define VEPU_REG_VP8_QUT_AC_Y1(x) (((x) & 0x3fff) << 16)
18 #define VEPU_REG_VP8_QUT_DC_CHR(x) (((x) & 0x3fff) << 0)
19 #define VEPU_REG_VP8_QUT_3RD(i) (0x008 + ((i) * 0x24))
20 #define VEPU_REG_VP8_QUT_AC_CHR(x) (((x) & 0x3fff) << 16)
21 #define VEPU_REG_VP8_QUT_AC_Y2(x) (((x) & 0x3fff) << 0)
22 #define VEPU_REG_VP8_QUT_4TH(i) (0x00c + ((i) * 0x24))
[all …]
/linux/drivers/dma/ti/
H A Dk3-udma.h12 #define UDMA_REV_REG 0x0
13 #define UDMA_PERF_CTL_REG 0x4
14 #define UDMA_EMU_CTL_REG 0x8
15 #define UDMA_PSIL_TO_REG 0x10
16 #define UDMA_UTC_CTL_REG 0x1c
17 #define UDMA_CAP_REG(i) (0x20 + ((i) * 4))
18 #define UDMA_RX_FLOW_ID_FW_OES_REG 0x80
19 #define UDMA_RX_FLOW_ID_FW_STATUS_REG 0x88
22 #define UDMA_CHAN_RT_CTL_REG 0x0
23 #define UDMA_CHAN_RT_SWTRIG_REG 0x8
[all …]
/linux/Documentation/devicetree/bindings/thermal/
H A Dthermal-sensor.yaml35 0 on sensor nodes with only a single sensor and at least 1 on nodes
37 enum: [0, 1]
57 reg = <0 0x0c263000 0 0x1ff>, /* TM */
58 <0 0x0c222000 0 0x1ff>; /* SROT */
68 reg = <0 0x0c265000 0 0x1ff>, /* TM */
69 <0 0x0c223000 0 0x1ff>; /* SROT */
/linux/drivers/gpu/host1x/hw/
H A Dhw_host1x01_sync.h29 * <x> value 'r' after being shifted to place its LSB at bit 0.
46 return 0x400 + id * REGISTER_STRIDE; in host1x_sync_syncpt_r()
52 return 0x40 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_cpu0_int_status_r()
58 return 0x60 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_int_disable_r()
64 return 0x68 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_int_enable_cpu0_r()
70 return 0x80 + channel * REGISTER_STRIDE; in host1x_sync_cf_setup_r()
76 return (r >> 0) & 0x1ff; in host1x_sync_cf_setup_base_v()
82 return (r >> 16) & 0x1ff; in host1x_sync_cf_setup_limit_v()
88 return 0xac; in host1x_sync_cmdproc_stop_r()
94 return 0xb0; in host1x_sync_ch_teardown_r()
[all …]
/linux/drivers/thermal/tegra/
H A Dtegra210-soctherm.c24 #define TEGRA210_THERMTRIP_ANY_EN_MASK (0x1 << 31)
25 #define TEGRA210_THERMTRIP_MEM_EN_MASK (0x1 << 30)
26 #define TEGRA210_THERMTRIP_GPU_EN_MASK (0x1 << 29)
27 #define TEGRA210_THERMTRIP_CPU_EN_MASK (0x1 << 28)
28 #define TEGRA210_THERMTRIP_TSENSE_EN_MASK (0x1 << 27)
29 #define TEGRA210_THERMTRIP_GPUMEM_THRESH_MASK (0x1ff << 18)
30 #define TEGRA210_THERMTRIP_CPU_THRESH_MASK (0x1ff << 9)
31 #define TEGRA210_THERMTRIP_TSENSE_THRESH_MASK 0x1ff
33 #define TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK (0x1ff << 18)
34 #define TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK (0x1ff << 9)
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/linux/drivers/net/dsa/
H A Dbcm_sf2_regs.h13 REG_SWITCH_CNTRL = 0,
36 #define MDIO_MASTER_SEL (1 << 0)
39 #define SF2_REV_MASK 0xffff
41 #define SWITCH_TOP_REV_MASK 0xffff
44 #define PHY_REVISION_MASK 0xffff
47 #define IDDQ_BIAS (1 << 0)
54 #define PHY_PHYAD_MASK 0x1F
57 #define CROSSBAR_BCM4908_INT_P7 0
59 #define CROSSBAR_BCM4908_EXT_SERDES 0
64 #define LED_CNTRL_NO_LINK_ENCODE_SHIFT 0
[all …]
/linux/drivers/clk/sifive/
H A Dsifive-prci.h28 #define PRCI_COREPLLCFG0_OFFSET 0x4
29 #define PRCI_COREPLLCFG0_DIVR_SHIFT 0
30 #define PRCI_COREPLLCFG0_DIVR_MASK (0x3f << PRCI_COREPLLCFG0_DIVR_SHIFT)
32 #define PRCI_COREPLLCFG0_DIVF_MASK (0x1ff << PRCI_COREPLLCFG0_DIVF_SHIFT)
34 #define PRCI_COREPLLCFG0_DIVQ_MASK (0x7 << PRCI_COREPLLCFG0_DIVQ_SHIFT)
36 #define PRCI_COREPLLCFG0_RANGE_MASK (0x7 << PRCI_COREPLLCFG0_RANGE_SHIFT)
38 #define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT)
40 #define PRCI_COREPLLCFG0_FSE_MASK (0x1 << PRCI_COREPLLCFG0_FSE_SHIFT)
42 #define PRCI_COREPLLCFG0_LOCK_MASK (0x1 << PRCI_COREPLLCFG0_LOCK_SHIFT)
45 #define PRCI_COREPLLCFG1_OFFSET 0x8
[all …]
/linux/drivers/mtd/nand/raw/ingenic/
H A Djz4740_ecc.c19 #define JZ_REG_NAND_ECC_CTRL 0x00
20 #define JZ_REG_NAND_DATA 0x04
21 #define JZ_REG_NAND_PAR0 0x08
22 #define JZ_REG_NAND_PAR1 0x0C
23 #define JZ_REG_NAND_PAR2 0x10
24 #define JZ_REG_NAND_IRQ_STAT 0x14
25 #define JZ_REG_NAND_IRQ_CTRL 0x18
26 #define JZ_REG_NAND_ERR(x) (0x1C + ((x) << 2))
32 #define JZ_NAND_ECC_CTRL_ENABLE BIT(0)
39 #define JZ_NAND_STATUS_ERROR BIT(0)
[all …]
/linux/drivers/video/fbdev/
H A Dau1200fb.h33 #define AU1200_LCD_ADDR 0xB5000000
64 uint32 reserved2[(0x0100-0x0058)/4];
77 uint32 reserved3[(0x0400-0x0180)/4];
79 volatile uint32 palette[(0x0800-0x0400)/4];
86 #define LCD_SCREEN_SX (0x07FF<<19)
87 #define LCD_SCREEN_SY (0x07FF<< 8)
90 #define LCD_SCREEN_PT (7<<0)
91 #define LCD_SCREEN_PT_TFT (0<<0)
94 #define LCD_SCREEN_PT_CSTN (1<<0)
95 #define LCD_SCREEN_PT_CDSTN (2<<0)
[all …]
/linux/drivers/memory/tegra/
H A Dmc.h15 #define MC_INTSTATUS 0x00
16 #define MC_INTMASK 0x04
17 #define MC_ERR_STATUS 0x08
18 #define MC_ERR_ADR 0x0c
19 #define MC_GART_ERROR_REQ 0x30
20 #define MC_EMEM_ADR_CFG 0x54
21 #define MC_DECERR_EMEM_OTHERS_STATUS 0x58
22 #define MC_SECURITY_VIOLATION_STATUS 0x74
23 #define MC_EMEM_ARB_CFG 0x90
24 #define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
[all …]
/linux/drivers/media/dvb-frontends/drx39xyj/
H A Ddrxj_map.h37 * Generated by: IDF:x 1.3.0
56 #define ATV_COMM_EXEC__A 0xC00000
58 #define ATV_COMM_EXEC__M 0x3
59 #define ATV_COMM_EXEC__PRE 0x0
60 #define ATV_COMM_EXEC_STOP 0x0
61 #define ATV_COMM_EXEC_ACTIVE 0x1
62 #define ATV_COMM_EXEC_HOLD 0x2
64 #define ATV_COMM_STATE__A 0xC00001
66 #define ATV_COMM_STATE__M 0xFFFF
67 #define ATV_COMM_STATE__PRE 0x0
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Di9xx_wm_regs.h9 #define DSPARB(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
10 #define DSPARB_CSTART_MASK (0x7f << 7)
12 #define DSPARB_BSTART_MASK (0x7f)
13 #define DSPARB_BSTART_SHIFT 0
15 #define DSPARB_AEND_SHIFT 0
16 #define DSPARB_SPRITEA_SHIFT_VLV 0
17 #define DSPARB_SPRITEA_MASK_VLV (0xff << 0)
19 #define DSPARB_SPRITEB_MASK_VLV (0xff << 8)
21 #define DSPARB_SPRITEC_MASK_VLV (0xff << 16)
23 #define DSPARB_SPRITED_MASK_VLV (0xff << 24)
[all …]
/linux/drivers/thermal/mediatek/
H A Dauxadc_thermal.c28 #define AUXADC_CON1_SET_V 0x008
29 #define AUXADC_CON1_CLR_V 0x00c
30 #define AUXADC_CON2_V 0x010
31 #define AUXADC_DATA(channel) (0x14 + (channel) * 4)
33 #define APMIXED_SYS_TS_CON0 0x600
34 #define APMIXED_SYS_TS_CON1 0x604
37 #define TEMP_MONCTL0 0x000
38 #define TEMP_MONCTL1 0x004
39 #define TEMP_MONCTL2 0x008
40 #define TEMP_MONIDET0 0x014
[all …]
/linux/include/video/
H A Dpmagb-b-fb.h16 #define PMAGB_B_ROM 0x000000 /* REX option ROM */
17 #define PMAGB_B_SFB 0x100000 /* SFB ASIC */
18 #define PMAGB_B_GP0 0x140000 /* general purpose output 0 */
19 #define PMAGB_B_GP1 0x180000 /* general purpose output 1 */
20 #define PMAGB_B_BT459 0x1c0000 /* Bt459 RAMDAC */
21 #define PMAGB_B_FBMEM 0x200000 /* frame buffer */
22 #define PMAGB_B_SIZE 0x400000 /* address space size */
25 #define SFB_REG_VID_HOR 0x64 /* video horizontal setup */
26 #define SFB_REG_VID_VER 0x68 /* video vertical setup */
27 #define SFB_REG_VID_BASE 0x6c /* video base address */
[all …]
/linux/drivers/crypto/intel/qat/qat_common/
H A Dicp_qat_hw_20_comp_defs.h7 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_MASK 0x1
10 ICP_QAT_HW_COMP_20_SCB_CONTROL_ENABLE = 0x0,
11 ICP_QAT_HW_COMP_20_SCB_CONTROL_DISABLE = 0x1,
18 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_MASK 0x1
21 ICP_QAT_HW_COMP_20_RMB_CONTROL_RESET_ALL = 0x0,
22 ICP_QAT_HW_COMP_20_RMB_CONTROL_RESET_FC_ONLY = 0x1,
29 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_MASK 0x3
32 ICP_QAT_HW_COMP_20_SOM_CONTROL_NORMAL_MODE = 0x0,
33 ICP_QAT_HW_COMP_20_SOM_CONTROL_REPLAY_MODE = 0x1,
34 ICP_QAT_HW_COMP_20_SOM_CONTROL_INPUT_CRC = 0x2,
[all …]
/linux/drivers/scsi/mvsas/
H A Dmv_64xx.c49 for (i = 0; i < MVS_SOC_PORTS; i++) { in mvs_64xx_phy_hacks()
51 mvs_write_port_vsr_data(mvi, i, 0x2F0); in mvs_64xx_phy_hacks()
55 mw32(MVS_GBL_PORT_TYPE, 0); in mvs_64xx_phy_hacks()
56 for (i = 0; i < mvi->chip->n_phy; i++) { in mvs_64xx_phy_hacks()
58 mvs_write_port_vsr_data(mvi, i, 0x90000000); in mvs_64xx_phy_hacks()
60 mvs_write_port_vsr_data(mvi, i, 0x50f2); in mvs_64xx_phy_hacks()
62 mvs_write_port_vsr_data(mvi, i, 0x0e); in mvs_64xx_phy_hacks()
131 printk(KERN_DEBUG "check SRS 0 %08X.\n", tmp); in mvs_64xx_clear_srs_irq()
137 printk(KERN_DEBUG "register set 0x%x was stopped.\n", in mvs_64xx_clear_srs_irq()
151 mw32(MVS_GBL_CTL, 0); in mvs_64xx_chip_reset()
[all …]
/linux/drivers/mtd/nand/raw/gpmi-nand/
H A Dgpmi-regs.h11 #define HW_GPMI_CTRL0 0x00000000
12 #define HW_GPMI_CTRL0_SET 0x00000004
13 #define HW_GPMI_CTRL0_CLR 0x00000008
14 #define HW_GPMI_CTRL0_TOG 0x0000000c
20 #define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0
21 #define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1
22 #define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
23 #define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3
26 #define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT 0x0
27 #define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT 0x1
[all …]
/linux/drivers/input/touchscreen/
H A Dtouchright.c30 #define TR_FORMAT_TOUCH_BIT 0x01
31 #define TR_FORMAT_STATUS_BYTE 0x40
36 #define TR_MIN_XC 0
37 #define TR_MAX_XC 0x1ff
38 #define TR_MIN_YC 0
39 #define TR_MAX_YC 0x1ff
61 if ((tr->data[0] & TR_FORMAT_STATUS_MASK) == TR_FORMAT_STATUS_BYTE) { in tr_interrupt()
68 tr->data[0] & TR_FORMAT_TOUCH_BIT); in tr_interrupt()
70 tr->idx = 0; in tr_interrupt()
120 input_dev->id.product = 0; in tr_connect()
[all …]
/linux/drivers/thermal/
H A Ddove_thermal.c17 #define DOVE_THERMAL_TEMP_MASK 0x1FF
20 #define PMU_TM_DISABLE_OFFS 0
21 #define PMU_TM_DISABLE_MASK (0x1 << PMU_TM_DISABLE_OFFS)
23 /* Dove Theraml Diode Control 0 Register */
24 #define PMU_TDC0_SW_RST_MASK (0x1 << 1)
26 #define PMU_TDC0_SEL_VCAL_MASK (0x3 << PMU_TDC0_SEL_VCAL_OFFS)
28 #define PMU_TDC0_REF_CAL_CNT_MASK (0x1FF << PMU_TDC0_REF_CAL_CNT_OFFS)
30 #define PMU_TDC0_AVG_NUM_MASK (0x7 << PMU_TDC0_AVG_NUM_OFFS)
33 #define PMU_TEMP_DIOD_CTRL1_REG 0x04
34 #define PMU_TDC1_TEMP_VALID_MASK (0x1 << 10)
[all …]
/linux/arch/sparc/math-emu/
H A Dmath_32.c86 #define FSQRTQ 0x02b /* v8 */
87 #define FADDQ 0x043 /* v8 */
88 #define FSUBQ 0x047 /* v8 */
89 #define FMULQ 0x04b /* v8 */
90 #define FDIVQ 0x04f /* v8 */
91 #define FDMULQ 0x06e /* v8 */
92 #define FQTOS 0x0c7 /* v8 */
93 #define FQTOD 0x0cb /* v8 */
94 #define FITOQ 0x0cc /* v8 */
95 #define FSTOQ 0x0cd /* v8 */
[all …]
/linux/sound/soc/codecs/
H A Dnau8822.h15 #define NAU8822_REG_RESET 0x00
16 #define NAU8822_REG_POWER_MANAGEMENT_1 0x01
17 #define NAU8822_REG_POWER_MANAGEMENT_2 0x02
18 #define NAU8822_REG_POWER_MANAGEMENT_3 0x03
19 #define NAU8822_REG_AUDIO_INTERFACE 0x04
20 #define NAU8822_REG_COMPANDING_CONTROL 0x05
21 #define NAU8822_REG_CLOCKING 0x06
22 #define NAU8822_REG_ADDITIONAL_CONTROL 0x07
23 #define NAU8822_REG_GPIO_CONTROL 0x08
24 #define NAU8822_REG_JACK_DETECT_CONTROL_1 0x09
[all …]
/linux/sound/soc/tegra/
H A Dtegra210_mbdrc.h16 #define TEGRA210_MBDRC_SOFT_RESET 0x4
17 #define TEGRA210_MBDRC_CG 0x8
18 #define TEGRA210_MBDRC_STATUS 0xc
19 #define TEGRA210_MBDRC_CFG 0x28
20 #define TEGRA210_MBDRC_CHANNEL_MASK 0x2c
21 #define TEGRA210_MBDRC_MASTER_VOL 0x30
22 #define TEGRA210_MBDRC_FAST_FACTOR 0x34
25 #define TEGRA210_MBDRC_FILTER_PARAM_STRIDE 0x4
27 #define TEGRA210_MBDRC_IIR_CFG 0x38
28 #define TEGRA210_MBDRC_IN_ATTACK 0x44
[all …]

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