Lines Matching +full:0 +full:x1ff
16 #define TEGRA210_MBDRC_SOFT_RESET 0x4
17 #define TEGRA210_MBDRC_CG 0x8
18 #define TEGRA210_MBDRC_STATUS 0xc
19 #define TEGRA210_MBDRC_CFG 0x28
20 #define TEGRA210_MBDRC_CHANNEL_MASK 0x2c
21 #define TEGRA210_MBDRC_MASTER_VOL 0x30
22 #define TEGRA210_MBDRC_FAST_FACTOR 0x34
25 #define TEGRA210_MBDRC_FILTER_PARAM_STRIDE 0x4
27 #define TEGRA210_MBDRC_IIR_CFG 0x38
28 #define TEGRA210_MBDRC_IN_ATTACK 0x44
29 #define TEGRA210_MBDRC_IN_RELEASE 0x50
30 #define TEGRA210_MBDRC_FAST_ATTACK 0x5c
31 #define TEGRA210_MBDRC_IN_THRESHOLD 0x68
32 #define TEGRA210_MBDRC_OUT_THRESHOLD 0x74
33 #define TEGRA210_MBDRC_RATIO_1ST 0x80
34 #define TEGRA210_MBDRC_RATIO_2ND 0x8c
35 #define TEGRA210_MBDRC_RATIO_3RD 0x98
36 #define TEGRA210_MBDRC_RATIO_4TH 0xa4
37 #define TEGRA210_MBDRC_RATIO_5TH 0xb0
38 #define TEGRA210_MBDRC_MAKEUP_GAIN 0xbc
39 #define TEGRA210_MBDRC_INIT_GAIN 0xc8
40 #define TEGRA210_MBDRC_GAIN_ATTACK 0xd4
41 #define TEGRA210_MBDRC_GAIN_RELEASE 0xe0
42 #define TEGRA210_MBDRC_FAST_RELEASE 0xec
43 #define TEGRA210_MBDRC_CFG_RAM_CTRL 0xf8
44 #define TEGRA210_MBDRC_CFG_RAM_DATA 0x104
52 #define TEGRA210_MBDRC_CFG_RMS_OFFSET_MASK (0x1ff << TEGRA210_MBDRC_CFG_RMS_OFFSET_SHIFT)
55 #define TEGRA210_MBDRC_CFG_PEAK_RMS_MASK (0x1 << TEGRA210_MBDRC_CFG_PEAK_RMS_SHIFT)
59 #define TEGRA210_MBDRC_CFG_FILTER_STRUCTURE_MASK (0x1 << TEGRA210_MBDRC_CFG_FILTER_STRUCTURE_SHIFT)
63 #define TEGRA210_MBDRC_CFG_SHIFT_CTRL_MASK (0x1f << TEGRA210_MBDRC_CFG_SHIFT_CTRL_SHIFT)
66 #define TEGRA210_MBDRC_CFG_FRAME_SIZE_MASK (0xf << TEGRA210_MBDRC_CFG_FRAME_SIZE_SHIFT)
68 #define TEGRA210_MBDRC_CFG_MBDRC_MODE_SHIFT 0
69 #define TEGRA210_MBDRC_CFG_MBDRC_MODE_MASK (0x3 << TEGRA210_MBDRC_CFG_MBDRC_MODE_SHIFT)
70 #define TEGRA210_MBDRC_CFG_MBDRC_MODE_BYPASS (0 << TEGRA210_MBDRC_CFG_MBDRC_MODE_SHIFT)
73 #define TEGRA210_MBDRC_CHANNEL_MASK_SHIFT 0
74 #define TEGRA210_MBDRC_CHANNEL_MASK_MASK (0xff << TEGRA210_MBDRC_CHANNEL_MASK_SHIFT)
83 #define TEGRA210_MBDRC_FAST_FACTOR_RELEASE_MASK (0xffff << TEGRA210_MBDRC_FAST_FACTOR_RELEASE_SHIF…
85 #define TEGRA210_MBDRC_FAST_FACTOR_ATTACK_SHIFT 0
86 #define TEGRA210_MBDRC_FAST_FACTOR_ATTACK_MASK (0xffff << TEGRA210_MBDRC_FAST_FACTOR_ATTACK_SHIFT)
89 #define TEGRA210_MBDRC_IIR_CFG_NUM_STAGES_SHIFT 0
90 #define TEGRA210_MBDRC_IIR_CFG_NUM_STAGES_MASK (0xf << TEGRA210_MBDRC_IIR_CFG_NUM_STAGES_SHIFT)
93 #define TEGRA210_MBDRC_IN_ATTACK_TC_SHIFT 0
94 #define TEGRA210_MBDRC_IN_ATTACK_TC_MASK (0xffffffff << TEGRA210_MBDRC_IN_ATTACK_TC_SHIFT)
97 #define TEGRA210_MBDRC_IN_RELEASE_TC_SHIFT 0
98 #define TEGRA210_MBDRC_IN_RELEASE_TC_MASK (0xffffffff << TEGRA210_MBDRC_IN_RELEASE_TC_SHIFT)
101 #define TEGRA210_MBDRC_FAST_ATTACK_TC_SHIFT 0
102 #define TEGRA210_MBDRC_FAST_ATTACK_TC_MASK (0xffffffff << TEGRA210_MBDRC_FAST_ATTACK_TC_SHIFT)
106 #define TEGRA210_MBDRC_THRESH_4TH_MASK (0xff << TEGRA210_MBDRC_THRESH_4TH_SHIFT)
109 #define TEGRA210_MBDRC_THRESH_3RD_MASK (0xff << TEGRA210_MBDRC_THRESH_3RD_SHIFT)
112 #define TEGRA210_MBDRC_THRESH_2ND_MASK (0xff << TEGRA210_MBDRC_THRESH_2ND_SHIFT)
114 #define TEGRA210_MBDRC_THRESH_1ST_SHIFT 0
115 #define TEGRA210_MBDRC_THRESH_1ST_MASK (0xff << TEGRA210_MBDRC_THRESH_1ST_SHIFT)
118 #define TEGRA210_MBDRC_RATIO_1ST_SHIFT 0
119 #define TEGRA210_MBDRC_RATIO_1ST_MASK (0xffff << TEGRA210_MBDRC_RATIO_1ST_SHIFT)
122 #define TEGRA210_MBDRC_RATIO_2ND_SHIFT 0
123 #define TEGRA210_MBDRC_RATIO_2ND_MASK (0xffff << TEGRA210_MBDRC_RATIO_2ND_SHIFT)
126 #define TEGRA210_MBDRC_RATIO_3RD_SHIFT 0
127 #define TEGRA210_MBDRC_RATIO_3RD_MASK (0xffff << TEGRA210_MBDRC_RATIO_3RD_SHIFT)
130 #define TEGRA210_MBDRC_RATIO_4TH_SHIFT 0
131 #define TEGRA210_MBDRC_RATIO_4TH_MASK (0xffff << TEGRA210_MBDRC_RATIO_4TH_SHIFT)
134 #define TEGRA210_MBDRC_RATIO_5TH_SHIFT 0
135 #define TEGRA210_MBDRC_RATIO_5TH_MASK (0xffff << TEGRA210_MBDRC_RATIO_5TH_SHIFT)
138 #define TEGRA210_MBDRC_MAKEUP_GAIN_SHIFT 0
139 #define TEGRA210_MBDRC_MAKEUP_GAIN_MASK (0x3f << TEGRA210_MBDRC_MAKEUP_GAIN_SHIFT)
142 #define TEGRA210_MBDRC_INIT_GAIN_SHIFT 0
143 #define TEGRA210_MBDRC_INIT_GAIN_MASK (0xffffffff << TEGRA210_MBDRC_INIT_GAIN_SHIFT)
146 #define TEGRA210_MBDRC_GAIN_ATTACK_SHIFT 0
147 #define TEGRA210_MBDRC_GAIN_ATTACK_MASK (0xffffffff << TEGRA210_MBDRC_GAIN_ATTACK_SHIFT)
150 #define TEGRA210_MBDRC_GAIN_RELEASE_SHIFT 0
151 #define TEGRA210_MBDRC_GAIN_RELEASE_MASK (0xffffffff << TEGRA210_MBDRC_GAIN_RELEASE_SHIFT)
154 #define TEGRA210_MBDRC_FAST_RELEASE_SHIFT 0
155 #define TEGRA210_MBDRC_FAST_RELEASE_MASK (0xffffffff << TEGRA210_MBDRC_FAST_RELEASE_SHIFT)
157 #define TEGRA210_MBDRC_RAM_CTRL_RW_READ 0
161 #define TEGRA210_MBDRC_RAM_CTRL_RAM_ADDR_MASK 0x1ff