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/linux/Documentation/devicetree/bindings/dma/
H A Dapm-xgene-dma.txt27 clocks = <&socplldiv2 0>;
28 reg = <0x0 0x1f27c000 0x0 0x1000>;
36 reg = <0x0 0x1f270000 0x0 0x10000>,
37 <0x0 0x1f200000 0x0 0x10000>,
38 <0x0 0x1b000000 0x0 0x400000>,
39 <0x0 0x1054a000 0x0 0x100>;
40 interrupts = <0x0 0x82 0x4>,
41 <0x0 0xb8 0x4>,
42 <0x0 0xb9 0x4>,
43 <0x0 0xba 0x4>,
[all …]
/linux/arch/mips/lantiq/falcon/
H A Dreset.c25 #define BOOT_REG_BASE (KSEG1 | 0x1F200000)
26 #define BOOT_PW1_REG (BOOT_REG_BASE | 0x20)
27 #define BOOT_PW2_REG (BOOT_REG_BASE | 0x24)
28 #define BOOT_PW1 0x4C545100
29 #define BOOT_PW2 0x0051544C
31 #define WDT_REG_BASE (KSEG1 | 0x1F8803F0)
32 #define WDT_PW1 0x00BE0000
33 #define WDT_PW2 0x00DC0000
40 ltq_w32(BOOT_PW1, (void *)BOOT_PW1_REG); /* 'LTQ\0' */ in machine_restart()
41 ltq_w32(BOOT_PW2, (void *)BOOT_PW2_REG); /* '\0QTL' */ in machine_restart()
[all …]
H A Dprom.c25 #define PART_MASK 0x0FFFF000
27 #define REV_MASK 0xF0000000
29 #define SREV_MASK 0x03C00000
31 #define TYPE_MASK 0x3C000000
34 #define BOOT_REG_BASE (KSEG1 | 0x1F200000)
35 #define BOOT_RVEC (BOOT_REG_BASE | 0x00)
36 #define BOOT_NVEC (BOOT_REG_BASE | 0x04)
37 #define BOOT_EVEC (BOOT_REG_BASE | 0x08)
61 sprintf(i->rev_type, "%c%d%d", (i->srev & 0x4) ? ('B') : ('A'), in ltq_soc_detect()
62 i->rev & 0x7, (i->srev & 0x3) + 1); in ltq_soc_detect()
[all …]
/linux/Documentation/devicetree/bindings/hwmon/
H A Dbaikal,bt1-pvt.yaml70 const: 0
76 default: 0
77 minimum: 0
95 reg = <0x1f200000 0x1000>;
96 #thermal-sensor-cells = <0>;
/linux/arch/arm64/boot/dts/apm/
H A Dapm-storm.dtsi16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0x0 0x000>;
23 cpu-release-addr = <0x1 0x0000fff8>;
29 reg = <0x0 0x001>;
31 cpu-release-addr = <0x1 0x0000fff8>;
37 reg = <0x0 0x100>;
39 cpu-release-addr = <0x1 0x0000fff8>;
45 reg = <0x0 0x101>;
47 cpu-release-addr = <0x1 0x0000fff8>;
[all …]
H A Dapm-shadowcat.dtsi16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0x0 0x000>;
23 cpu-release-addr = <0x1 0x0000fff8>;
26 clocks = <&pmd0clk 0>;
31 reg = <0x0 0x001>;
33 cpu-release-addr = <0x1 0x0000fff8>;
36 clocks = <&pmd0clk 0>;
41 reg = <0x0 0x100>;
43 cpu-release-addr = <0x1 0x0000fff8>;
[all …]