Lines Matching +full:0 +full:x1f200000
16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0x0 0x000>;
23 cpu-release-addr = <0x1 0x0000fff8>;
29 reg = <0x0 0x001>;
31 cpu-release-addr = <0x1 0x0000fff8>;
37 reg = <0x0 0x100>;
39 cpu-release-addr = <0x1 0x0000fff8>;
45 reg = <0x0 0x101>;
47 cpu-release-addr = <0x1 0x0000fff8>;
53 reg = <0x0 0x200>;
55 cpu-release-addr = <0x1 0x0000fff8>;
61 reg = <0x0 0x201>;
63 cpu-release-addr = <0x1 0x0000fff8>;
69 reg = <0x0 0x300>;
71 cpu-release-addr = <0x1 0x0000fff8>;
77 reg = <0x0 0x301>;
79 cpu-release-addr = <0x1 0x0000fff8>;
82 xgene_L2_0: l2-cache-0 {
108 reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */
109 <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */
110 <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */
111 <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */
112 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
124 interrupts = <1 0 0xff08>, /* Secure Phys IRQ */
125 <1 13 0xff08>, /* Non-secure Phys IRQ */
126 <1 14 0xff08>, /* Virt IRQ */
127 <1 15 0xff08>; /* Hyp IRQ */
133 interrupts = <1 12 0xff04>;
141 dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;
151 clocks = <&refclk 0>;
153 reg = <0x0 0x17000100 0x0 0x1000>;
155 type = <0>;
161 clocks = <&refclk 0>;
163 reg = <0x0 0x17000120 0x0 0x1000>;
171 clocks = <&socpll 0>;
181 clocks = <&socplldiv2 0>;
182 reg = <0x0 0x17000000 0x0 0x2000>;
184 divider-offset = <0x164>;
185 divider-width = <0x5>;
186 divider-shift = <0x0>;
193 clocks = <&socplldiv2 0>;
194 reg = <0x0 0x1f2ac000 0x0 0x1000
195 0x0 0x17000000 0x0 0x2000>;
197 csr-offset = <0x0>;
198 csr-mask = <0x2>;
199 enable-offset = <0x8>;
200 enable-mask = <0x2>;
201 divider-offset = <0x178>;
202 divider-width = <0x8>;
203 divider-shift = <0x0>;
210 clocks = <&socplldiv2 0>;
212 reg = <0x0 0x17000000 0x0 0x1000>;
214 divider-offset = <0x238>;
215 divider-width = <0x9>;
216 divider-shift = <0x0>;
223 clocks = <ðclk 0>;
224 reg = <0x0 0x1702c000 0x0 0x1000>;
232 clocks = <&socplldiv2 0>;
233 reg = <0x0 0x1f21c000 0x0 0x1000>;
235 csr-mask = <0xa>;
236 enable-mask = <0xf>;
243 clocks = <&socplldiv2 0>;
244 reg = <0x0 0x1f61c000 0x0 0x1000>;
246 csr-mask = <0x3>;
254 clocks = <&socplldiv2 0>;
255 reg = <0x0 0x1f62c000 0x0 0x1000>;
257 csr-mask = <0x3>;
264 clocks = <&socplldiv2 0>;
265 reg = <0x0 0x1f21c000 0x0 0x1000>;
269 csr-offset = <0x4>;
270 csr-mask = <0x00>;
271 enable-offset = <0x0>;
272 enable-mask = <0x06>;
278 clocks = <&socplldiv2 0>;
279 reg = <0x0 0x1f22c000 0x0 0x1000>;
283 csr-offset = <0x4>;
284 csr-mask = <0x3a>;
285 enable-offset = <0x0>;
286 enable-mask = <0x06>;
292 clocks = <&socplldiv2 0>;
293 reg = <0x0 0x1f23c000 0x0 0x1000>;
297 csr-offset = <0x4>;
298 csr-mask = <0x3a>;
299 enable-offset = <0x0>;
300 enable-mask = <0x06>;
306 clocks = <&socplldiv2 0>;
307 reg = <0x0 0x1f21c000 0x0 0x1000>;
310 csr-offset = <0x4>;
311 csr-mask = <0x05>;
312 enable-offset = <0x0>;
313 enable-mask = <0x39>;
319 clocks = <&socplldiv2 0>;
320 reg = <0x0 0x1f22c000 0x0 0x1000>;
323 csr-offset = <0x4>;
324 csr-mask = <0x05>;
325 enable-offset = <0x0>;
326 enable-mask = <0x39>;
332 clocks = <&socplldiv2 0>;
333 reg = <0x0 0x1f23c000 0x0 0x1000>;
336 csr-offset = <0x4>;
337 csr-mask = <0x05>;
338 enable-offset = <0x0>;
339 enable-mask = <0x39>;
345 clocks = <&socplldiv2 0>;
346 reg = <0x0 0x17000000 0x0 0x2000>;
348 csr-offset = <0xc>;
349 csr-mask = <0x2>;
350 enable-offset = <0x10>;
351 enable-mask = <0x2>;
358 clocks = <&socplldiv2 0>;
359 reg = <0x0 0x17000000 0x0 0x2000>;
361 csr-offset = <0xc>;
362 csr-mask = <0x10>;
363 enable-offset = <0x10>;
364 enable-mask = <0x10>;
372 clocks = <&socplldiv2 0>;
373 reg = <0x0 0x1f2bc000 0x0 0x1000>;
382 clocks = <&socplldiv2 0>;
383 reg = <0x0 0x1f2cc000 0x0 0x1000>;
392 clocks = <&socplldiv2 0>;
393 reg = <0x0 0x1f2dc000 0x0 0x1000>;
402 clocks = <&socplldiv2 0>;
403 reg = <0x0 0x1f50c000 0x0 0x1000>;
412 clocks = <&socplldiv2 0>;
413 reg = <0x0 0x1f51c000 0x0 0x1000>;
421 clocks = <&socplldiv2 0>;
422 reg = <0x0 0x1f27c000 0x0 0x1000>;
431 reg = <0x00 0x79000000 0x0 0x900000>;
432 interrupts = < 0x0 0x10 0x4
433 0x0 0x11 0x4
434 0x0 0x12 0x4
435 0x0 0x13 0x4
436 0x0 0x14 0x4
437 0x0 0x15 0x4
438 0x0 0x16 0x4
439 0x0 0x17 0x4
440 0x0 0x18 0x4
441 0x0 0x19 0x4
442 0x0 0x1a 0x4
443 0x0 0x1b 0x4
444 0x0 0x1c 0x4
445 0x0 0x1d 0x4
446 0x0 0x1e 0x4
447 0x0 0x1f 0x4>;
452 reg = <0x0 0x17000000 0x0 0x400>;
458 offset = <0x14>;
459 mask = <0x1>;
464 reg = <0x0 0x7e200000 0x0 0x1000>;
469 reg = <0x0 0x7e700000 0x0 0x1000>;
474 reg = <0x0 0x7e720000 0x0 0x1000>;
479 reg = <0x0 0x1054a000 0x0 0x20>;
484 reg = <0x0 0x7e000000 0x0 0x10>;
497 reg = <0x0 0x78800000 0x0 0x100>;
498 interrupts = <0x0 0x20 0x4>,
499 <0x0 0x21 0x4>,
500 <0x0 0x27 0x4>;
504 reg = <0x0 0x7e800000 0x0 0x1000>;
505 memory-controller = <0>;
510 reg = <0x0 0x7e840000 0x0 0x1000>;
516 reg = <0x0 0x7e880000 0x0 0x1000>;
522 reg = <0x0 0x7e8c0000 0x0 0x1000>;
528 reg = <0x0 0x7c000000 0x0 0x200000>;
529 pmd-controller = <0>;
534 reg = <0x0 0x7c200000 0x0 0x200000>;
540 reg = <0x0 0x7c400000 0x0 0x200000>;
546 reg = <0x0 0x7c600000 0x0 0x200000>;
552 reg = <0x0 0x7e600000 0x0 0x1000>;
557 reg = <0x0 0x7e930000 0x0 0x1000>;
569 reg = <0x0 0x78810000 0x0 0x1000>;
570 interrupts = <0x0 0x22 0x4>;
574 reg = <0x0 0x7e610000 0x0 0x1000>;
579 reg = <0x0 0x7e940000 0x0 0x1000>;
584 reg = <0x0 0x7e710000 0x0 0x1000>;
585 enable-bit-index = <0>;
590 reg = <0x0 0x7e730000 0x0 0x1000>;
596 reg = <0x0 0x7e810000 0x0 0x1000>;
597 enable-bit-index = <0>;
602 reg = <0x0 0x7e850000 0x0 0x1000>;
608 reg = <0x0 0x7e890000 0x0 0x1000>;
614 reg = <0x0 0x7e8d0000 0x0 0x1000>;
626 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
627 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
629 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
630 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000 /* mem */
631 0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */
632 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
633 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
634 bus-range = <0x00 0xff>;
635 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
636 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x4
637 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x4
638 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x4
639 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x4>;
641 clocks = <&pcie0clk 0>;
652 reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */
653 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
655 ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000 /* io */
656 0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000 /* mem */
657 0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */
658 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
659 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
660 bus-range = <0x00 0xff>;
661 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
662 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x4
663 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x4
664 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x4
665 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x4>;
667 clocks = <&pcie1clk 0>;
678 reg = < 0x00 0x1f2d0000 0x0 0x00010000 /* Controller registers */
679 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
681 ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000 /* io */
682 0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000 /* mem */
683 0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */
684 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
685 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
686 bus-range = <0x00 0xff>;
687 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
688 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x4
689 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x4
690 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x4
691 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x4>;
693 clocks = <&pcie2clk 0>;
704 reg = < 0x00 0x1f500000 0x0 0x00010000 /* Controller registers */
705 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
707 ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */
708 0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000 /* mem */
709 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
710 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
711 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
712 bus-range = <0x00 0xff>;
713 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
714 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x4
715 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x4
716 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x4
717 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x4>;
719 clocks = <&pcie3clk 0>;
730 reg = < 0x00 0x1f510000 0x0 0x00010000 /* Controller registers */
731 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
733 ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */
734 0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000 /* mem */
735 0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */
736 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
737 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
738 bus-range = <0x00 0xff>;
739 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
740 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x4
741 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x4
742 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x4
743 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x4>;
745 clocks = <&pcie4clk 0>;
751 reg = <0x0 0x10540000 0x0 0xa000>;
753 interrupts = <0x0 0x0 0x4>,
754 <0x0 0x1 0x4>,
755 <0x0 0x2 0x4>,
756 <0x0 0x3 0x4>,
757 <0x0 0x4 0x4>,
758 <0x0 0x5 0x4>,
759 <0x0 0x6 0x4>,
760 <0x0 0x7 0x4>;
765 mboxes = <&mailbox 0>;
776 reg = <0 0x1c020000 0x0 0x1000>;
780 interrupts = <0x0 0x4c 0x4>;
786 reg = <0 0x1c021000 0x0 0x1000>;
790 interrupts = <0x0 0x4d 0x4>;
796 reg = <0 0x1c022000 0x0 0x1000>;
800 interrupts = <0x0 0x4e 0x4>;
806 reg = <0 0x1c023000 0x0 0x1000>;
810 interrupts = <0x0 0x4f 0x4>;
815 reg = <0x0 0x1c000000 0x0 0x100>;
816 interrupts = <0x0 0x49 0x4>;
820 clocks = <&sdioclk 0>, <&ahbclk 0>;
825 reg = <0x0 0x1701c000 0x0 0x40>;
832 reg = <0x0 0x1c024000 0x0 0x1000>;
834 #size-cells = <0>;
836 porta: gpio-controller@0 {
841 reg = <0>;
848 #size-cells = <0>;
850 reg = <0x0 0x10512000 0x0 0x1000>;
851 interrupts = <0 0x44 0x4>;
853 clocks = <&ahbclk 0>;
854 bus_num = <0>;
859 reg = <0x0 0x1f21a000 0x0 0x100>;
861 clocks = <&sataphy1clk 0>;
869 reg = <0x0 0x1f22a000 0x0 0x100>;
871 clocks = <&sataphy2clk 0>;
879 reg = <0x0 0x1f23a000 0x0 0x100>;
881 clocks = <&sataphy3clk 0>;
889 reg = <0x0 0x1a000000 0x0 0x1000>,
890 <0x0 0x1f210000 0x0 0x1000>,
891 <0x0 0x1f21d000 0x0 0x1000>,
892 <0x0 0x1f21e000 0x0 0x1000>,
893 <0x0 0x1f217000 0x0 0x1000>;
894 interrupts = <0x0 0x86 0x4>;
897 clocks = <&sata01clk 0>;
898 phys = <&phy1 0>;
904 reg = <0x0 0x1a400000 0x0 0x1000>,
905 <0x0 0x1f220000 0x0 0x1000>,
906 <0x0 0x1f22d000 0x0 0x1000>,
907 <0x0 0x1f22e000 0x0 0x1000>,
908 <0x0 0x1f227000 0x0 0x1000>;
909 interrupts = <0x0 0x87 0x4>;
912 clocks = <&sata23clk 0>;
913 phys = <&phy2 0>;
919 reg = <0x0 0x1a800000 0x0 0x1000>,
920 <0x0 0x1f230000 0x0 0x1000>,
921 <0x0 0x1f23d000 0x0 0x1000>,
922 <0x0 0x1f23e000 0x0 0x1000>;
923 interrupts = <0x0 0x88 0x4>;
926 clocks = <&sata45clk 0>;
927 phys = <&phy3 0>;
935 reg = <0x0 0x19000000 0x0 0x100000>;
936 interrupts = <0x0 0x89 0x4>;
944 reg = <0x0 0x19800000 0x0 0x100000>;
945 interrupts = <0x0 0x8a 0x4>;
952 reg = <0x0 0x17001000 0x0 0x400>;
955 interrupts = <0x0 0x28 0x1>,
956 <0x0 0x29 0x1>,
957 <0x0 0x2a 0x1>,
958 <0x0 0x2b 0x1>,
959 <0x0 0x2c 0x1>,
960 <0x0 0x2d 0x1>;
968 reg = <0x0 0x10510000 0x0 0x400>;
969 interrupts = <0x0 0x46 0x4>;
971 clocks = <&rtcclk 0>;
977 #size-cells = <0>;
978 reg = <0x0 0x17020000 0x0 0xd100>;
979 clocks = <&menetclk 0>;
985 reg = <0x0 0x17020000 0x0 0xd100>,
986 <0x0 0x17030000 0x0 0xc300>,
987 <0x0 0x10000000 0x0 0x200>;
989 interrupts = <0x0 0x3c 0x4>;
991 clocks = <&menetclk 0>;
999 #size-cells = <0>;
1002 reg = <0x3>;
1011 reg = <0x0 0x1f210000 0x0 0xd100>,
1012 <0x0 0x1f200000 0x0 0xc300>,
1013 <0x0 0x1b000000 0x0 0x200>;
1015 interrupts = <0x0 0xa0 0x4>,
1016 <0x0 0xa1 0x4>;
1018 clocks = <&sge0clk 0>;
1027 reg = <0x0 0x1f210030 0x0 0xd100>,
1028 <0x0 0x1f200000 0x0 0xc300>,
1029 <0x0 0x1b000000 0x0 0x8000>;
1031 interrupts = <0x0 0xac 0x4>,
1032 <0x0 0xad 0x4>;
1043 reg = <0x0 0x1f610000 0x0 0xd100>,
1044 <0x0 0x1f600000 0x0 0xc300>,
1045 <0x0 0x18000000 0x0 0x200>;
1047 interrupts = <0x0 0x60 0x4>,
1048 <0x0 0x61 0x4>,
1049 <0x0 0x62 0x4>,
1050 <0x0 0x63 0x4>,
1051 <0x0 0x64 0x4>,
1052 <0x0 0x65 0x4>,
1053 <0x0 0x66 0x4>,
1054 <0x0 0x67 0x4>;
1055 channel = <0>;
1057 clocks = <&xge0clk 0>;
1066 reg = <0x0 0x1f620000 0x0 0xd100>,
1067 <0x0 0x1f600000 0x0 0xc300>,
1068 <0x0 0x18000000 0x0 0x8000>;
1070 interrupts = <0x0 0x6c 0x4>,
1071 <0x0 0x6d 0x4>;
1074 clocks = <&xge1clk 0>;
1082 reg = <0x0 0x10520000 0x0 0x100>;
1083 interrupts = <0x0 0x41 0x4>;
1084 clocks = <&rngpkaclk 0>;
1090 reg = <0x0 0x1f270000 0x0 0x10000>,
1091 <0x0 0x1f200000 0x0 0x10000>,
1092 <0x0 0x1b000000 0x0 0x400000>,
1093 <0x0 0x1054a000 0x0 0x100>;
1094 interrupts = <0x0 0x82 0x4>,
1095 <0x0 0xb8 0x4>,
1096 <0x0 0xb9 0x4>,
1097 <0x0 0xba 0x4>,
1098 <0x0 0xbb 0x4>;
1100 clocks = <&dmaclk 0>;