/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/ |
H A D | imx53-tx53.dtsi | 55 reg = <0x70000000 0>; 69 clock-frequency = <0>; 75 #clock-cells = <0>; 82 pinctrl-0 = <&pinctrl_gpio_key>; 95 pinctrl-0 = <&pinctrl_stk5led>; 124 pinctrl-0 = <&pinctrl_can_xcvr>; 134 pinctrl-0 = <&pinctrl_usbh1_vbus>; 145 pinctrl-0 = <&pinctrl_usbotg_vbus>; 167 pinctrl-0 = <&pinctrl_ssi1>; 173 pinctrl-0 = <&pinctrl_can1>; [all …]
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H A D | imx53-tx53-x13x.dts | 64 pwms = <&pwm2 0 500000 0>; 67 0 1 2 3 4 5 6 7 8 9 84 pwms = <&pwm1 0 500000 0>; 87 0 1 2 3 4 5 6 7 8 9 125 pinctrl-0 = <&pinctrl_i2c3>; 133 reg = <0x0a>; 134 #sound-dai-cells = <0>; 145 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 146 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 147 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 [all …]
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H A D | imx53-tx53-x03x.dts | 60 pinctrl-0 = <&pinctrl_rgb24_vga1>; 80 hsync-active = <0>; 81 vsync-active = <0>; 83 pixelclk-active = <0>; 96 hsync-active = <0>; 97 vsync-active = <0>; 99 pixelclk-active = <0>; 112 hsync-active = <0>; 113 vsync-active = <0>; 115 pixelclk-active = <0>; [all …]
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H A D | imxrt1050-pinfunc.h | 10 #define IMX_PAD_SION 0x40000000 17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0 18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0 19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1 20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0 21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0 22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0 24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0 25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0 26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1 [all …]
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H A D | imx50-pinfunc.h | 13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0 14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0 15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0 16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0 17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0 18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0 19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0 20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0 21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0 22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0 [all …]
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H A D | imx6sl-pinfunc.h | 13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0 14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0 15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0 16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0 17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0 18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0 19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0 20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0 21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0 22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0 [all …]
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H A D | imxrt1170-pinfunc.h | 10 #define IMX_PAD_SION 0x40000000 17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0 18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0 19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0 20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0 21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0 22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0 23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0 24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0 26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0 [all …]
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/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/ |
H A D | dm814.h | 8 #define DM814_CLKCTRL_OFFSET 0x0 12 #define DM814_USB_OTG_HS_CLKCTRL DM814_CLKCTRL_INDEX(0x58) 15 #define DM814_UART1_CLKCTRL DM814_CLKCTRL_INDEX(0x150) 16 #define DM814_UART2_CLKCTRL DM814_CLKCTRL_INDEX(0x154) 17 #define DM814_UART3_CLKCTRL DM814_CLKCTRL_INDEX(0x158) 18 #define DM814_GPIO1_CLKCTRL DM814_CLKCTRL_INDEX(0x15c) 19 #define DM814_GPIO2_CLKCTRL DM814_CLKCTRL_INDEX(0x160) 20 #define DM814_I2C1_CLKCTRL DM814_CLKCTRL_INDEX(0x164) 21 #define DM814_I2C2_CLKCTRL DM814_CLKCTRL_INDEX(0x168) 22 #define DM814_WD_TIMER_CLKCTRL DM814_CLKCTRL_INDEX(0x18c) [all …]
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H A D | dm816.h | 8 #define DM816_CLKCTRL_OFFSET 0x0 12 #define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58) 15 #define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150) 16 #define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154) 17 #define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158) 18 #define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c) 19 #define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160) 20 #define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164) 21 #define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168) 22 #define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170) [all …]
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/freebsd/sys/dev/ath/ath_hal/ar5416/ |
H A D | ar5416_gpio.c | 52 * 5 bits per GPIO pin. Bits 0..4 for 1st pin in that mux, in cfgOutputMux() 60 * PRDATA[4:0] <= gpio_output_mux[0]; in cfgOutputMux() 62 * <==== Bit 4 is used by both gpio_output_mux[0] [1]. in cfgOutputMux() 70 (0x1f << gpio_shift)); in cfgOutputMux() 73 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); in cfgOutputMux() 74 tmp &= ~(0x1f << gpio_shift); in cfgOutputMux() 88 #define N(a) (sizeof(a) / sizeof(a[0])) in ar5416GpioCfgOutput() 187 return 0xffffffff; in ar5416GpioGet() 200 return ((bits & AR_GPIO_BIT(gpio)) != 0); in ar5416GpioGet() 246 /* 0 == interrupt on pin high */ in ar5416GpioSetIntr()
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/freebsd/sys/i386/conf/ |
H A D | GENERIC.hints | 1 hint.fdc.0.at="isa" 2 hint.fdc.0.port="0x3F0" 3 hint.fdc.0.irq="6" 4 hint.fdc.0.drq="2" 5 hint.fd.0.at="fdc0" 6 hint.fd.0.drive="0" 9 hint.ata.0.at="isa" 10 hint.ata.0.port="0x1F0" 11 hint.ata.0.irq="14" 13 hint.ata.1.port="0x170" [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/marvell/ |
H A D | ac5-98dx25xx.dtsi | 21 #size-cells = <0>; 34 cpu0: cpu@0 { 37 reg = <0x0 0x0>; 45 reg = <0x0 0x100>; 85 /* 16M internal register @ 0x7f00_0000 */ 86 ranges = <0x0 0x0 0x7f000000 0x1000000>; 91 reg = <0x12000 0x100>; 101 reg = <0x12100 0x100>; 111 reg = <0x12200 0x100>; 121 reg = <0x12300 0x100>; [all …]
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/freebsd/sys/contrib/device-tree/src/arm/ti/omap/ |
H A D | dra72x-mmc-iodelay.dtsi | 37 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 38 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 39 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 40 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ 41 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ 42 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ 48 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 49 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 50 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 51 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ [all …]
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H A D | dra74x-mmc-iodelay.dtsi | 35 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 36 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 37 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 38 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ 39 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ 40 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ 46 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 47 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 48 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 49 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/freescale/ |
H A D | imx8mp-pinfunc.h | 13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0 14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0 15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0 16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0 17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0 18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0 19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0 20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0 21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0 22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0 [all …]
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H A D | imx8mq-pinfunc.h | 15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0… 16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0… 17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0… 18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0… 19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0… 20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0… 21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0… 22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0… 23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0… 24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0… [all …]
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H A D | imx8mm-pinfunc.h | 14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0… 15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0… 16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0… 17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0… 18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0… 19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0… 20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0… 21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0… 22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0… 23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0… [all …]
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/freebsd/sys/contrib/device-tree/src/arm/nxp/vf/ |
H A D | vf610-pinfunc.h | 14 #define ALT0 0x0 15 #define ALT1 0x1 16 #define ALT2 0x2 17 #define ALT3 0x3 18 #define ALT4 0x4 19 #define ALT5 0x5 20 #define ALT6 0x6 21 #define ALT7 0x7 24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0 25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0 [all …]
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/freebsd/contrib/file/magic/Magdir/ |
H A D | audio | 11 0 string .snd Sun/NeXT audio data: 45 >16 belong >0 %d Hz 49 0 lelong 0x0064732E DEC audio data: 83 >16 lelong >0 %d Hz 86 0 string MThd Standard MIDI data 91 >12 beshort&0x7fff x at 1/%d 92 >12 beshort&0x8000 >0 SMPTE 94 0 string CTMF Creative Music (CMF) data 96 0 string SBI SoundBlaster instrument data 98 0 string Creative\ Voice\ File Creative Labs voice data [all …]
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/freebsd/sys/dev/rtwn/rtl8188e/ |
H A D | r88e_reg.h | 29 #define R88E_BB_PAD_CTRL 0x064 30 #define R88E_HIMR 0x0b0 31 #define R88E_HISR 0x0b4 32 #define R88E_HIMRE 0x0b8 33 #define R88E_HISRE 0x0bc 34 #define R88E_XCK_OUT_CTRL 0x07c 36 #define R88E_32K_CTRL 0x194 37 #define R88E_HMEBOX_EXT(idx) (0x1f0 + (idx) * 4) 39 #define R88E_TXPKTBUF_BCNQ1_BDNY 0x457 40 #define R88E_MACID_NO_LINK 0x484 [all …]
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/freebsd/usr.sbin/cxgbetool/ |
H A D | reg_defs_t4vf.c | 7 { "SGE_KDOORBELL", 0x000, 0 }, 10 { "PIDX", 0, 14 }, 11 { "SGE_GTS", 0x004, 0 }, 15 { "CIDXInc", 0, 12 }, 17 { NULL, 0, 0 } 21 { "SGE_VF_KDOORBELL", 0x000, 0 }, 25 { "PIDX", 0, 13 }, 26 { "SGE_VF_GTS", 0x004, 0 }, 30 { "CIDXInc", 0, 12 }, 32 { NULL, 0, 0 } [all …]
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/freebsd/sys/arm/freescale/imx/ |
H A D | imx6_anatopreg.h | 32 #define IMX6_ANALOG_CCM_PLL_ARM 0x000 33 #define IMX6_ANALOG_CCM_PLL_ARM_SET 0x004 34 #define IMX6_ANALOG_CCM_PLL_ARM_CLR 0x008 35 #define IMX6_ANALOG_CCM_PLL_ARM_TOG 0x00C 36 #define IMX6_ANALOG_CCM_PLL_ARM_DIV_MASK 0x7F 39 #define IMX6_ANALOG_CCM_PLL_ARM_CLK_SRC_MASK (0x03 << 16) 40 #define IMX6_ANALOG_CCM_PLL_USB1 0x010 41 #define IMX6_ANALOG_CCM_PLL_USB1_SET 0x014 42 #define IMX6_ANALOG_CCM_PLL_USB1_CLR 0x018 43 #define IMX6_ANALOG_CCM_PLL_USB1_TOG 0x01C [all …]
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/freebsd/sys/sys/ |
H A D | disk_zone.h | 70 #define DISK_ZONE_MODE_NONE 0x00 71 #define DISK_ZONE_MODE_HOST_AWARE 0x01 72 #define DISK_ZONE_MODE_DRIVE_MANAGED 0x02 73 #define DISK_ZONE_MODE_HOST_MANAGED 0x04 75 #define DISK_ZONE_DISK_URSWRZ 0x001 76 #define DISK_ZONE_OPT_SEQ_SET 0x002 77 #define DISK_ZONE_OPT_NONSEQ_SET 0x004 78 #define DISK_ZONE_MAX_SEQ_SET 0x008 79 #define DISK_ZONE_RZ_SUP 0x010 80 #define DISK_ZONE_OPEN_SUP 0x020 [all …]
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/freebsd/contrib/elftoolchain/libpe/ |
H A D | pe.h | 75 #define IMAGE_FILE_MACHINE_UNKNOWN 0x0 /* not specified */ 76 #define IMAGE_FILE_MACHINE_AM33 0x1d3 /* Matsushita AM33 */ 77 #define IMAGE_FILE_MACHINE_AMD64 0x8664 /* x86-64 */ 78 #define IMAGE_FILE_MACHINE_ARM 0x1c0 /* ARM LE */ 79 #define IMAGE_FILE_MACHINE_ARMNT 0x1c4 /* ARMv7(or higher) Thumb */ 80 #define IMAGE_FILE_MACHINE_ARM64 0xaa64 /* ARMv8 64-bit */ 81 #define IMAGE_FILE_MACHINE_EBC 0xebc /* EFI byte code */ 82 #define IMAGE_FILE_MACHINE_I386 0x14c /* x86 */ 83 #define IMAGE_FILE_MACHINE_IA64 0x200 /* IA64 */ 84 #define IMAGE_FILE_MACHINE_M32R 0x9041 /* Mitsubishi M32R LE */ [all …]
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/freebsd/sys/powerpc/include/ |
H A D | trap.h | 39 #define EXC_RSVD 0x0000 /* Reserved */ 40 #define EXC_RST 0x0100 /* Reset; all but IBM4xx */ 41 #define EXC_MCHK 0x0200 /* Machine Check */ 42 #define EXC_DSI 0x0300 /* Data Storage Interrupt */ 43 #define EXC_DSE 0x0380 /* Data Segment Interrupt */ 44 #define EXC_ISI 0x0400 /* Instruction Storage Interrupt */ 45 #define EXC_ISE 0x0480 /* Instruction Segment Interrupt */ 46 #define EXC_EXI 0x0500 /* External Interrupt */ 47 #define EXC_ALI 0x0600 /* Alignment Interrupt */ 48 #define EXC_PGM 0x0700 /* Program Interrupt */ [all …]
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