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/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dqcom,ebi2.txt24 CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
25 CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
26 CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
27 CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
28 CS4 GPIO132 0x1c800000-0x1d000000 (8MB)
29 CS5 GPIO131 0x1c000000-0x1c800000 (8MB)
58 ranges = <0 0x0 0x1a800000 0x00800000>,
59 <1 0x0 0x1b000000 0x00800000>,
60 <2 0x0 0x1b800000 0x00800000>,
61 <3 0x0 0x1d000000 0x08000000>,
[all …]
H A Dqcom,ebi2.yaml31 CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
32 CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
33 CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
34 CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
35 CS4 GPIO132 0x1c800000-0x1d000000 (8MB)
36 CS5 GPIO131 0x1c000000-0x1c800000 (8MB)
105 "^.*@[0-5],[0-9a-f]+$":
120 actually 1, so a value of 0 will still yield 1 recovery cycle.
121 minimum: 0
129 asserted. With a hold of 1 (value = 0), the CS stays active
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/mediatek/
H A Dmediatek,bdpsys.txt22 reg = <0 0x1c000000 0 0x1000>;
/freebsd/sys/dev/ath/ath_hal/ar9002/
H A Dar9287an.h22 #define AR9287_AN_RF2G3_CH0 0x7808
23 #define AR9287_AN_RF2G3_CH1 0x785c
24 #define AR9287_AN_RF2G3_DB1 0xE0000000
26 #define AR9287_AN_RF2G3_DB2 0x1C000000
28 #define AR9287_AN_RF2G3_OB_CCK 0x03800000
30 #define AR9287_AN_RF2G3_OB_PSK 0x00700000
32 #define AR9287_AN_RF2G3_OB_QAM 0x000E0000
34 #define AR9287_AN_RF2G3_OB_PAL_OFF 0x0001C000
37 #define AR9287_AN_TXPC0 0x7898
38 #define AR9287_AN_TXPC0_TXPCMODE 0x0000C000
[all …]
H A Dar9285an.h25 #define AR9285_AN_RF2G1 0x7820
27 #define AR9285_AN_RF2G1_ENPACAL 0x00000800
29 #define AR9285_AN_RF2G1_PDPADRV1 0x02000000
31 #define AR9285_AN_RF2G1_PDPADRV2 0x01000000
33 #define AR9285_AN_RF2G1_PDPAOUT 0x00800000
36 #define AR9285_AN_RF2G2 0x7824
38 #define AR9285_AN_RF2G2_OFFCAL 0x00001000
41 #define AR9285_AN_RF2G3 0x7828
43 #define AR9285_AN_RF2G3_PDVCCOMP 0x02000000
45 #define AR9285_AN_RF2G3_OB_0 0x00E00000
[all …]
H A Dar9285phy.h31 #define AR9285_AN_RF2G1 0x7820
32 #define AR9285_AN_RF2G1_ENPACAL 0x00000800
34 #define AR9285_AN_RF2G1_PDPADRV1 0x02000000
36 #define AR9285_AN_RF2G1_PDPADRV2 0x01000000
38 #define AR9285_AN_RF2G1_PDPAOUT 0x00800000
41 #define AR9285_AN_RF2G2 0x7824
42 #define AR9285_AN_RF2G2_OFFCAL 0x00001000
45 #define AR9285_AN_RF2G3 0x7828
46 #define AR9285_AN_RF2G3_PDVCCOMP 0x02000000
48 #define AR9285_AN_RF2G3_OB_0 0x00E00000
[all …]
/freebsd/sys/contrib/device-tree/src/mips/ralink/
H A Dmt7621-gnubee-gb-pc1.dts13 memory@0 {
15 reg = <0x00000000 0x1c000000>,
16 <0x20000000 0x04000000>;
57 flash@0 {
61 reg = <0>;
65 partition@0 {
67 reg = <0x
[all...]
H A Dmt7621-gnubee-gb-pc2.dts13 memory@0 {
15 reg = <0x00000000 0x1c000000>,
16 <0x20000000 0x04000000>;
77 flash@0 {
81 reg = <0>;
85 partition@0 {
87 reg = <0x
[all...]
/freebsd/sys/arm/freescale/imx/
H A Dimx_gptreg.h33 #define IMX_GPT_CR 0x0000 /* Control Register R/W */
38 #define GPT_CR_OM3_MASK 0x1c000000
40 #define GPT_CR_OM2_MASK 0x03800000
42 #define GPT_CR_OM1_MASK 0x00700000
43 #define GPT_CR_OMX_NONE 0
49 #define GPT_CR_IM2_MASK 0x000c0000
51 #define GPT_CR_IM1_MASK 0x00030000
52 #define GPT_CR_IMX_NONE 0
59 #define GPT_CR_CLKSRC_NONE (0 << 6)
70 #define GPT_CR_EN (1 << 0)
[all …]
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Darm,pl172.txt11 first address cell and it may accept values 0..N-1
88 Example for pl172 with nor flash on chip select 0 shown below.
92 reg = <0x40005000 0x1000>;
97 ranges = <0 0 0x1c000000 0x1000000
98 1 0 0x1d000000 0x1000000
99 2 0 0x1e000000 0x1000000
100 3 0 0x1f000000 0x1000000>;
107 mpmc,cs = <0>;
110 mpmc,write-enable-delay = <0>;
111 mpmc,output-enable-delay = <0>;
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5210/
H A Dar5210desc.h31 uint32_t ds_ctl0; /* DMA control 0 */
33 uint32_t ds_status0; /* DMA status 0 */
40 #define AR_FrameLen 0x00000fff /* frame length */
41 #define AR_HdrLen 0x0003f000 /* header length */
43 #define AR_XmitRate 0x003c0000 /* txrate */
45 #define AR_Rate_6M 0xb
46 #define AR_Rate_9M 0xf
47 #define AR_Rate_12M 0xa
48 #define AR_Rate_18M 0xe
49 #define AR_Rate_24M 0x9
[all …]
/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dsnps,dw-apb-ssi.yaml144 default: 0
163 "^.*@[0-9a-f]+$":
169 minimum: 0
185 reg = <0xfff00000 0x1000>;
187 #size-cells = <0>;
188 interrupts = <0 154 4>;
191 cs-gpios = <&gpio0 13 0>,
192 <&gpio0 14 0>;
203 reg = <0x1f040100 0x900>,
204 <0x1c000000 0x1000000>;
[all …]
/freebsd/sys/contrib/device-tree/src/mips/mti/
H A Dsead3.dts4 /memreserve/ 0x00000000 0x00001000; // reserved
5 /memreserve/ 0x00001000 0x000ef000; // ROM data
6 /memreserve/ 0x000f0000 0x004cc000; // reserved
26 cpu@0 {
33 reg = <0x0 0x08000000>;
45 reg = <0x1b1c0000 0x20000>;
61 reg = <0x1b200000 0x1000>;
64 interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
71 reg = <0x1c000000 0x2000000>;
81 user-fs@0 {
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/arm/
H A Dfoundation-v8.dtsi12 /memreserve/ 0x80000000 0x00010000;
34 #size-cells = <0>;
36 cpu0: cpu@0 {
39 reg = <0x0 0x0>;
45 reg = <0x0 0x1>;
51 reg = <0x0 0x2>;
57 reg = <0x0 0x3>;
70 reg = <0x00000000 0x80000000 0 0x80000000>,
71 <0x00000008 0x80000000 0 0x80000000>;
98 reg = <0x0 0x2a440000 0 0x1000>,
[all …]
H A Drtsm_ve-motherboard.dtsi13 #clock-cells = <0>;
20 #clock-cells = <0>;
27 #clock-cells = <0>;
49 #clock-cells = <0>;
55 arm,vexpress-sysreg,func = <5 0>;
60 arm,vexpress-sysreg,func = <7 0>;
65 arm,vexpress-sysreg,func = <8 0>;
70 arm,vexpress-sysreg,func = <9 0>;
75 arm,vexpress-sysreg,func = <11 0>;
83 ranges = <0 0x8000000 0 0x8000000 0x18000000>;
[all …]
H A Djuno-motherboard.dtsi13 #clock-cells = <0>;
20 #clock-cells = <0>;
27 #clock-cells = <0>;
34 #clock-cells = <0>;
55 gpios = <&iofpga_gpio0 0 0x4>;
62 gpios = <&iofpga_gpio0 1 0x4>;
69 gpios = <&iofpga_gpio0 2 0x4>;
76 gpios = <&iofpga_gpio0 3 0x4>;
83 gpios = <&iofpga_gpio0 4 0x4>;
90 gpios = <&iofpga_gpio0 5 0x4>;
[all …]
H A Dvexpress-v2m-rs1.dtsi23 v2m_fixed_3v3: fixed-regulator-0 {
33 #clock-cells = <0>;
40 #clock-cells = <0>;
47 #clock-cells = <0>;
57 gpios = <&v2m_led_gpios 0 0>;
63 gpios = <&v2m_led_gpios 1 0>;
69 gpios = <&v2m_led_gpios 2 0>;
75 gpios = <&v2m_led_gpios 3 0>;
81 gpios = <&v2m_led_gpios 4 0>;
87 gpios = <&v2m_led_gpios 5 0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Dintegratorcp.dts19 #size-cells = <0>;
21 cpu@0 {
30 reg = <0>;
35 operating-points = <50000 0
36 48000 0>;
51 #clock-cells = <0>;
58 #clock-cells = <0>;
67 #clock-cells = <0>;
74 #clock-cells = <0>;
81 #clock-cells = <0>;
[all …]
H A Dvexpress-v2m-rs1.dtsi33 #clock-cells = <0>;
40 #clock-cells = <0>;
47 #clock-cells = <0>;
57 gpios = <&v2m_led_gpios 0 0>;
63 gpios = <&v2m_led_gpios 1 0>;
69 gpios = <&v2m_led_gpios 2 0>;
75 gpios = <&v2m_led_gpios 3 0>;
81 gpios = <&v2m_led_gpios 4 0>;
87 gpios = <&v2m_led_gpios 5 0>;
93 gpios = <&v2m_led_gpios 6 0>;
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5416/
H A Dar5416reg.h27 #define AR_MIRT 0x0020 /* interrupt rate threshold */
28 #define AR_TIMT 0x0028 /* Tx Interrupt mitigation threshold */
29 #define AR_RIMT 0x002C /* Rx Interrupt mitigation threshold */
30 #define AR_GTXTO 0x0064 /* global transmit timeout */
31 #define AR_GTTM 0x0068 /* global transmit timeout mode */
32 #define AR_CST 0x006C /* carrier sense timeout */
33 #define AR_MAC_LED 0x1f04 /* LED control */
34 #define AR_WA 0x4004 /* PCIE work-arounds */
35 #define AR_PCIE_PM_CTRL 0x4014
36 #define AR_AHB_MODE 0x4024 /* AHB mode for dma */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-msm8660.dtsi18 #size-cells = <0>;
20 cpu@0 {
24 reg = <0>;
45 reg = <0x0 0x0>;
56 #clock-cells = <0>;
63 #clock-cells = <0>;
70 #clock-cells = <0>;
86 reg = < 0x02080000 0x1000 >,
87 < 0x02081000 0x1000 >;
92 interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhi6220-hikey.dts32 * 0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using
33 * 0x05f0,1000 - 0x05f0,1fff: Reboot reason
34 * 0x06df,f000 - 0x06df,ffff: Mailbox message data
35 * 0x0740,f000 - 0x0740,ffff: MCU firmware section
36 * 0x21f0,0000 - 0x21ff,ffff: pstore/ramoops buffer
37 * 0x3e00,0000 - 0x3fff,ffff: OP-TEE
39 memory@0 {
41 reg = <0x00000000 0x00000000 0x00000000 0x05e00000>,
42 <0x00000000 0x05f00000 0x00000000 0x00001000>,
43 <0x00000000 0x05f02000 0x00000000 0x00efd000>,
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Dam335x-nano.dts14 cpu@0 {
21 reg = <0x80000000 0x10000000>; /* 256 MB */
29 gpios = <&gpio1 5 0>;
37 pinctrl-0 = <&misc_pins>;
162 pinctrl-0 = <&uart0_pins>;
168 pinctrl-0 = <&uart1_pins>;
179 pinctrl-0 = <&uart2_pins>;
189 pinctrl-0 = <&uart3_pins>;
200 pinctrl-0 = <&uart4_pins>;
211 pinctrl-0 = <&uart5_pins>;
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300desc.h94 #define AR_desc_len 0x000000ff
95 #define AR_rx_priority 0x00000100
96 #define AR_tx_qcu_num 0x00000f00
98 #define AR_ctrl_stat 0x00004000
100 #define AR_tx_rx_desc 0x00008000
102 #define AR_desc_id 0xffff0000
113 #define AR_buf_len 0x0fff0000
117 #define AR_tx_desc_id 0xffff0000
119 #define AR_tx_ptr_chk_sum 0x0000ffff
122 #define AR_frame_len 0x00000fff
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/lpc/
H A Dlpc18xx.dtsi19 #define LPC_PIN(port, pin) (0x##port * 32 + pin)
28 #size-cells = <0>;
30 cpu@0 {
33 reg = <0x0>;
41 #clock-cells = <0>;
47 #clock-cells = <0>;
53 #clock-cells = <0>;
54 clock-frequency = <0>;
60 #clock-cells = <0>;
61 clock-frequency = <0>;
[all...]

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