Lines Matching +full:0 +full:x1c000000
94 #define AR_desc_len 0x000000ff
95 #define AR_rx_priority 0x00000100
96 #define AR_tx_qcu_num 0x00000f00
98 #define AR_ctrl_stat 0x00004000
100 #define AR_tx_rx_desc 0x00008000
102 #define AR_desc_id 0xffff0000
113 #define AR_buf_len 0x0fff0000
117 #define AR_tx_desc_id 0xffff0000
119 #define AR_tx_ptr_chk_sum 0x0000ffff
122 #define AR_frame_len 0x00000fff
123 #define AR_virt_more_frag 0x00001000
124 #define AR_tx_ctl_rsvd00 0x00002000
125 #define AR_low_rx_chain 0x00004000
126 #define AR_tx_clear_retry 0x00008000
127 #define AR_xmit_power0 0x003f0000
129 #define AR_rts_enable 0x00400000
130 #define AR_veol 0x00800000
131 #define AR_clr_dest_mask 0x01000000
132 #define AR_tx_bf0 0x02000000
133 #define AR_tx_bf1 0x04000000
134 #define AR_tx_bf2 0x08000000
135 #define AR_tx_bf3 0x10000000
136 #define AR_TxBfSteered 0x1e000000 /* for tx_bf*/
137 #define AR_tx_intr_req 0x20000000
138 #define AR_dest_idx_valid 0x40000000
139 #define AR_cts_enable 0x80000000
142 #define AR_tx_ctl_rsvd02 0x000001ff
143 #define AR_paprd_chain_mask 0x00000e00
145 #define AR_tx_more 0x00001000
146 #define AR_dest_idx 0x000fe000
148 #define AR_frame_type 0x00f00000
150 #define AR_no_ack 0x01000000
151 #define AR_insert_ts 0x02000000
152 #define AR_corrupt_fcs 0x04000000
153 #define AR_ext_only 0x08000000
154 #define AR_ext_and_ctl 0x10000000
155 #define AR_more_aggr 0x20000000
156 #define AR_is_aggr 0x40000000
157 #define AR_more_rifs 0x80000000
158 #define AR_loc_mode 0x00000100 /* Positioning bit in TX desc */
161 #define AR_burst_dur 0x00007fff
162 #define AR_burst_dur_S 0
163 #define AR_dur_update_ena 0x00008000
164 #define AR_xmit_data_tries0 0x000f0000
166 #define AR_xmit_data_tries1 0x00f00000
168 #define AR_xmit_data_tries2 0x0f000000
170 #define AR_xmit_data_tries3 0xf0000000
174 #define AR_xmit_rate0 0x000000ff
175 #define AR_xmit_rate0_S 0
176 #define AR_xmit_rate1 0x0000ff00
178 #define AR_xmit_rate2 0x00ff0000
180 #define AR_xmit_rate3 0xff000000
184 #define AR_packet_dur0 0x00007fff
185 #define AR_packet_dur0_S 0
186 #define AR_rts_cts_qual0 0x00008000
187 #define AR_packet_dur1 0x7fff0000
189 #define AR_rts_cts_qual1 0x80000000
192 #define AR_packet_dur2 0x00007fff
193 #define AR_packet_dur2_S 0
194 #define AR_rts_cts_qual2 0x00008000
195 #define AR_packet_dur3 0x7fff0000
197 #define AR_rts_cts_qual3 0x80000000
200 #define AR_aggr_len 0x0000ffff
201 #define AR_aggr_len_S 0
202 #define AR_tx_ctl_rsvd60 0x00030000
203 #define AR_pad_delim 0x03fc0000
205 #define AR_encr_type 0x1c000000
207 #define AR_tx_dc_ap_sta_sel 0x40000000
208 #define AR_tx_ctl_rsvd61 0xc0000000
209 #define AR_calibrating 0x40000000
210 #define AR_ldpc 0x80000000
213 #define AR_2040_0 0x00000001
214 #define AR_gi0 0x00000002
215 #define AR_chain_sel0 0x0000001c
217 #define AR_2040_1 0x00000020
218 #define AR_gi1 0x00000040
219 #define AR_chain_sel1 0x00000380
221 #define AR_2040_2 0x00000400
222 #define AR_gi2 0x00000800
223 #define AR_chain_sel2 0x00007000
225 #define AR_2040_3 0x00008000
226 #define AR_gi3 0x00010000
227 #define AR_chain_sel3 0x000e0000
229 #define AR_rts_cts_rate 0x0ff00000
231 #define AR_stbc0 0x10000000
232 #define AR_stbc1 0x20000000
233 #define AR_stbc2 0x40000000
234 #define AR_stbc3 0x80000000
237 #define AR_tx_ant0 0x00ffffff
238 #define AR_tx_ant_sel0 0x80000000
239 #define AR_RTS_HTC_TRQ 0x10000000 /* bit 28 for rts_htc_TRQ*/ /*for tx_bf*/
240 #define AR_not_sounding 0x20000000
241 #define AR_ness 0xc0000000
245 #define AR_tx_ant1 0x00ffffff
246 #define AR_xmit_power1 0x3f000000
248 #define AR_tx_ant_sel1 0x80000000
249 #define AR_ness1 0xc0000000
253 #define AR_tx_ant2 0x00ffffff
254 #define AR_xmit_power2 0x3f000000
256 #define AR_tx_ant_sel2 0x80000000
257 #define AR_ness2 0xc0000000
261 #define AR_tx_ant3 0x00ffffff
262 #define AR_xmit_power3 0x3f000000
264 #define AR_tx_ant_sel3 0x80000000
265 #define AR_ness3 0xc0000000
273 #define AR_tx_status_rsvd 0x0000ffff
276 #define AR_tx_rssi_ant00 0x000000ff
277 #define AR_tx_rssi_ant00_S 0
278 #define AR_tx_rssi_ant01 0x0000ff00
280 #define AR_tx_rssi_ant02 0x00ff0000
282 #define AR_tx_status_rsvd00 0x3f000000
283 #define AR_tx_ba_status 0x40000000
284 #define AR_tx_status_rsvd01 0x80000000
287 #define AR_frm_xmit_ok 0x00000001
288 #define AR_excessive_retries 0x00000002
289 #define AR_fifounderrun 0x00000004
290 #define AR_filtered 0x00000008
291 #define AR_rts_fail_cnt 0x000000f0
293 #define AR_data_fail_cnt 0x00000f00
295 #define AR_virt_retry_cnt 0x0000f000
297 #define AR_tx_delim_underrun 0x00010000
298 #define AR_tx_data_underrun 0x00020000
299 #define AR_desc_cfg_err 0x00040000
300 #define AR_tx_timer_expired 0x00080000
301 #define AR_tx_status_rsvd10 0xfff00000
304 #define AR_tx_rssi_ant10 0x000000ff
305 #define AR_tx_rssi_ant10_S 0
306 #define AR_tx_rssi_ant11 0x0000ff00
308 #define AR_tx_rssi_ant12 0x00ff0000
310 #define AR_tx_rssi_combined 0xff000000
314 #define AR_tx_done 0x00000001
315 #define AR_seq_num 0x00001ffe
317 #define AR_tx_status_rsvd80 0x0001e000
318 #define AR_tx_op_exceeded 0x00020000
319 #define AR_tx_status_rsvd81 0x001c0000
320 #define AR_TXBFStatus 0x001c0000
322 #define AR_tx_bf_bw_mismatch 0x00040000
323 #define AR_tx_bf_stream_miss 0x00080000
324 #define AR_final_tx_idx 0x00600000
326 #define AR_tx_bf_dest_miss 0x00800000
327 #define AR_tx_bf_expired 0x01000000
328 #define AR_power_mgmt 0x02000000
329 #define AR_tx_status_rsvd83 0x0c000000
330 #define AR_tx_tid 0xf0000000
332 #define AR_tx_fast_ts 0x08000000 /* 27th bit for locationing */
340 #define AR_rx_rssi_ant00 0x000000ff
341 #define AR_rx_rssi_ant00_S 0
342 #define AR_rx_rssi_ant01 0x0000ff00
344 #define AR_rx_rssi_ant02 0x00ff0000
346 #define AR_rx_rate 0xff000000
350 #define AR_data_len 0x00000fff
351 #define AR_data_len_S 0
352 #define AR_rx_more 0x00001000
353 #define AR_num_delim 0x003fc000
355 #define AR_hw_upload_data 0x00400000
357 #define AR_rx_status_rsvd10 0xff800000
361 #define AR_gi 0x00000001
362 #define AR_2040 0x00000002
363 #define AR_parallel40 0x00000004
365 #define AR_rx_stbc 0x00000008
366 #define AR_rx_not_sounding 0x00000010
367 #define AR_rx_ness 0x00000060
369 #define AR_hw_upload_data_valid 0x00000080
371 #define AR_rx_antenna 0xffffff00
375 #define AR_rx_rssi_ant10 0x000000ff
376 #define AR_rx_rssi_ant10_S 0
377 #define AR_rx_rssi_ant11 0x0000ff00
379 #define AR_rx_rssi_ant12 0x00ff0000
381 #define AR_rx_rssi_combined 0xff000000
397 #define AR_rx_done 0x00000001
398 #define AR_rx_frame_ok 0x00000002
399 #define AR_crc_err 0x00000004
400 #define AR_decrypt_crc_err 0x00000008
401 #define AR_phyerr 0x00000010
402 #define AR_michael_err 0x00000020
403 #define AR_pre_delim_crc_err 0x00000040
404 #define AR_apsd_trig 0x00000080
405 #define AR_rx_key_idx_valid 0x00000100
406 #define AR_key_idx 0x0000fe00
408 #define AR_phy_err_code 0x0000ff00
410 #define AR_rx_more_aggr 0x00010000
411 #define AR_rx_aggr 0x00020000
412 #define AR_post_delim_crc_err 0x00040000
413 #define AR_rx_status_rsvd71 0x01f80000
414 #define AR_hw_upload_data_type 0x06000000
416 #define AR_position_bit 0x08000000 /* positioning bit */
417 #define AR_hi_rx_chain 0x10000000
418 #define AR_rx_first_aggr 0x20000000
419 #define AR_decrypt_busy_err 0x40000000
420 #define AR_key_miss 0x80000000
427 #define RXCTL_OFFSET(ah) 0
428 #define RXCTL_NUMWORDS(ah) 0
453 AR_rts_cts_qual##_index : 0))
455 #define not_two_stream_rate(_rate) (((_rate) >0x8f) || ((_rate)<0x88))
458 ((( not_two_stream_rate((_series)[0].Rate) && (not_two_stream_rate((_series)[1].Rate)|| \
461 ? AR_ldpc : 0)
464 ((_series)[_index].RateFlags & HAL_RATESERIES_2040 ? AR_2040_##_index : 0) \
465 |((_series)[_index].RateFlags & HAL_RATESERIES_HALFGI ? AR_gi##_index : 0) \
466 |((_series)[_index].RateFlags & HAL_RATESERIES_STBC ? AR_stbc##_index : 0) \
483 ((1<<0x0b)|(1<<0x0f)|(1<<0x0a)|(1<<0x0e)|(1<<0x09)|(1<<0x0d)|\
484 (1<<0x08)|(1<<0x0c)|(1<<0x1b)|(1<<0x1a)|(1<<0x1e)|(1<<0x19)|\
485 (1<<0x1d)|(1<<0x18)|(1<<0x1c))