Home
last modified time | relevance | path

Searched +full:0 +full:x1f000 (Results 1 – 25 of 65) sorted by relevance

123

/linux/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_mpc.c65 mpcc->dpp_id = 0xf; in mpc201_init_mpcc()
68 mpcc->blnd_cfg.global_alpha = 0xff; in mpc201_init_mpcc()
69 mpcc->blnd_cfg.global_gain = 0xff; in mpc201_init_mpcc()
71 mpcc->blnd_cfg.bottom_gain_mode = 0; in mpc201_init_mpcc()
72 mpcc->blnd_cfg.top_gain = 0x1f000; in mpc201_init_mpcc()
73 mpcc->blnd_cfg.bottom_inside_gain = 0x1f000; in mpc201_init_mpcc()
74 mpcc->blnd_cfg.bottom_outside_gain = 0x1f000; in mpc201_init_mpcc()
120 mpc201->mpcc_in_use_mask = 0; in dcn201_mpc_construct()
123 for (i = 0; i < MAX_MPCC; i++) in dcn201_mpc_construct()
/linux/arch/arm64/boot/dts/realtek/
H A Drtd1295-mele-v9.dts17 reg = <0x1f000 0x7ffe1000>; /* boot ROM to 2 GiB */
H A Drtd1295-probox2-ava.dts17 reg = <0x1f000 0x7ffe1000>; /* boot ROM to 2 GiB */
H A Drtd1296-ds418.dts16 reg = <0x1f000 0x7ffe1000>; /* boot ROM to 2 GiB */
H A Drtd1295-xnano-x5.dts16 reg = <0x1f000 0x3ffe1000>; /* boot ROM to 1 GiB or 2 GiB */
H A Drtd1293-ds418j.dts16 reg = <0x1f000 0x3ffe1000>; /* boot ROM to 1 GiB */
H A Drtd1295-zidoo-x9s.dts16 reg = <0x1f000 0x7ffe1000>; /* boot ROM to 2 GiB */
H A Drtd129x.dtsi8 /memreserve/ 0x0000000000000000 0x000000000001f000;
9 /memreserve/ 0x000000000001f000 0x00000000000e1000;
10 /memreserve/ 0x0000000001b00000 0x00000000004be000;
26 reg = <0x1f000 0x1000>;
30 reg = <0x1ffe000 0x4000>;
34 reg = <0x10100000 0xf00000>;
47 #clock-cells = <0>;
51 soc@0 {
55 ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */
57 <0x80000000 0x80000000 0x80000000>;
[all …]
/linux/arch/powerpc/math-emu/
H A Dfcmpu.c16 int code[4] = { (1 << 3), (1 << 1), (1 << 2), (1 << 0) }; in fcmpu()
34 __FPU_FPSCR &= ~(0x1f000); in fcmpu()
44 return 0; in fcmpu()
H A Dfcmpo.c16 int code[4] = { (1 << 3), (1 << 1), (1 << 2), (1 << 0) }; in fcmpo()
37 __FPU_FPSCR &= ~(0x1f000); in fcmpo()
/linux/drivers/gpu/drm/amd/display/dc/mpc/dcn20/
H A Ddcn20_mpc.c46 #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
66 REG_SET(MPCC_TOP_GAIN[mpcc_id], 0, MPCC_TOP_GAIN, blnd_cfg->top_gain); in mpc2_update_blending()
67 REG_SET(MPCC_BOT_GAIN_INSIDE[mpcc_id], 0, MPCC_BOT_GAIN_INSIDE, blnd_cfg->bottom_inside_gain); in mpc2_update_blending()
68 REG_SET(MPCC_BOT_GAIN_OUTSIDE[mpcc_id], 0, MPCC_BOT_GAIN_OUTSIDE, blnd_cfg->bottom_outside_gain); in mpc2_update_blending()
79 int denorm_mode = 0; in mpc2_set_denorm()
142 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_output_csc()
182 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_output_csc()
198 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_ocsc_default()
241 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_ocsc_default()
278 REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0, in mpc20_power_on_ogam_lut()
[all …]
/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Ddcore0_sync_mngr_mstr_if_axuser_masks.h24 #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID_WR_SHIFT 0
25 #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID_WR_MASK 0x3FF
27 #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID_RD_MASK 0x3FF0000
30 #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_MMU_BP_WR_SHIFT 0
31 #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_MMU_BP_WR_MASK 0x1
33 #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_MMU_BP_RD_MASK 0x10
36 #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_STRONG_ORDER_WR_SHIFT 0
37 #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_STRONG_ORDER_WR_MASK 0x1
39 #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_STRONG_ORDER_RD_MASK 0x10
42 #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_NO_SNOOP_WR_SHIFT 0
[all …]
H A Darc_farm_kdma_ctx_axuser_masks.h24 #define ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_WR_SHIFT 0
25 #define ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_WR_MASK 0x3FF
27 #define ARC_FARM_KDMA_CTX_AXUSER_HB_ASID_RD_MASK 0x3FF0000
30 #define ARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP_WR_SHIFT 0
31 #define ARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP_WR_MASK 0x1
33 #define ARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP_RD_MASK 0x10
36 #define ARC_FARM_KDMA_CTX_AXUSER_HB_STRONG_ORDER_WR_SHIFT 0
37 #define ARC_FARM_KDMA_CTX_AXUSER_HB_STRONG_ORDER_WR_MASK 0x1
39 #define ARC_FARM_KDMA_CTX_AXUSER_HB_STRONG_ORDER_RD_MASK 0x10
42 #define ARC_FARM_KDMA_CTX_AXUSER_HB_NO_SNOOP_WR_SHIFT 0
[all …]
/linux/arch/sh/mm/
H A Dtlb-sh3.c47 /* conveniently, we want all the software flags to be 0 anyway */ in __update_tlb()
66 addr = MMU_TLB_ADDRESS_ARRAY | (page & 0x1F000); in local_flush_tlb_one()
67 data = (page & 0xfffe0000) | asid; /* VALID bit is off */ in local_flush_tlb_one()
74 for (i = 0; i < ways; i++) in local_flush_tlb_one()
91 status |= 0x04; in local_flush_tlb_all()
/linux/Documentation/devicetree/bindings/phy/
H A Dmarvell,comphy-cp110.yaml32 - description: Lane 0 (USB3/GbE) registers (Armada 3700)
47 const: 0
62 '^phy@[0-5]$':
121 reg = <0x120000 0x6000>;
125 #size-cells = <0>;
128 phy@0 {
129 reg = <0>;
142 reg = <0x18300 0x300>,
143 <0x1F000 0x400>,
144 <0x5C000 0x400>,
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.c98 } else if (addr->quad_part == 0) { in gpu_addr_to_uma()
170 struct tg_color black_color = {0}; in dcn201_init_blank()
173 uint32_t otg_active_width = 0, otg_active_height = 0; in dcn201_init_blank()
197 0); in dcn201_init_blank()
211 /* bit 23:0 in register map to bit 47:24 in address */ in read_mmhub_vm_setup()
259 for (i = 0; i < dc->link_count; i++) { in dcn201_init_hw()
268 if (hws->fb_offset.quad_part == 0) in dcn201_init_hw()
272 for (i = 0; i < res_pool->timing_generator_count; i++) { in dcn201_init_hw()
280 for (i = 0; i < res_pool->timing_generator_count; i++) { in dcn201_init_hw()
287 for (i = 0; i < res_pool->pipe_count; i++) { in dcn201_init_hw()
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dtrinityd.h30 #define CG_CGTT_LOCAL_0 0x0
31 #define CG_CGTT_LOCAL_1 0x1
34 #define SMU_SCLK_DPM_STATE_0_CNTL_0 0x1f000
35 # define STATE_VALID(x) ((x) << 0)
36 # define STATE_VALID_MASK (0xff << 0)
37 # define STATE_VALID_SHIFT 0
39 # define CLK_DIVIDER_MASK (0xff << 8)
42 # define VID_MASK (0xff << 16)
45 # define LVRT_MASK (0xff << 24)
47 #define SMU_SCLK_DPM_STATE_0_CNTL_1 0x1f004
[all …]
/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8851b_rfk_table.c8 RTW89_DECL_RFK_WM(0xc210, 0x003fc000, 0x80),
9 RTW89_DECL_RFK_WM(0xc224, 0x003fc000, 0x80),
10 RTW89_DECL_RFK_WM(0xc0f8, 0x30000000, 0x3),
11 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
12 RTW89_DECL_RFK_WM(0x030c, 0x1f000000, 0x1f),
13 RTW89_DECL_RFK_WM(0x032c, 0xc0000000, 0x0),
14 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x0),
15 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x1),
16 RTW89_DECL_RFK_WM(0x032c, BIT(16), 0x0),
17 RTW89_DECL_RFK_WM(0x032c, BIT(20), 0x1),
[all …]
/linux/arch/arc/boot/dts/
H A Daxs10x_mb.dtsi17 ranges = <0x00000000 0x0 0xe0000000 0x10000000>;
23 reg = <0x11220 0x4>;
28 reg = <0x100a0 0x10>;
30 #clock-cells = <0>;
37 #clock-cells = <0>;
43 #clock-cells = <0>;
49 #clock-cells = <0>;
62 #clock-cells = <0>;
68 reg = <0x10080 0x10>, <0x110 0x10>;
69 #clock-cells = <0>;
[all …]
/linux/drivers/media/rc/
H A Dir-rc5-decoder.c50 return 0; in ir_rc5_decode()
61 return 0; in ir_rc5_decode()
88 return 0; in ir_rc5_decode()
117 return 0; in ir_rc5_decode()
119 xdata = (data->bits & 0x0003F) >> 0; in ir_rc5_decode()
120 command = (data->bits & 0x00FC0) >> 6; in ir_rc5_decode()
121 system = (data->bits & 0x1F000) >> 12; in ir_rc5_decode()
122 toggle = (data->bits & 0x20000) ? 1 : 0; in ir_rc5_decode()
123 command += (data->bits & 0x40000) ? 0 : 0x40; in ir_rc5_decode()
132 return 0; in ir_rc5_decode()
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm63138.dtsi23 #size-cells = <0>;
25 cpu@0 {
29 reg = <0>;
46 #clock-cells = <0>;
54 #clock-cells = <0>;
63 #clock-cells = <0>;
72 #clock-cells = <0>;
80 ranges = <0 0x80000000 0x784000>;
86 reg = <0x1d000 0x1000>;
92 interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
[all …]
/linux/drivers/tty/vt/
H A Dgen_ucs_width_table.py21 0x200B, # ZERO WIDTH SPACE
22 0x200C, # ZERO WIDTH NON-JOINER
23 0x200D, # ZERO WIDTH JOINER
24 0x2060, # WORD JOINER
25 0xFEFF # ZERO WIDTH NO-BREAK SPACE (BOM)
34 (0x1F3FB, 0x1F3FF), # Emoji modifiers (skin tones)
37 (0xFE00, 0xFE0F), # Variation Selectors 1-16
42 (0x2640, 0x2640), # Female sign
43 (0x2642, 0x2642), # Male sign
44 (0x26A7, 0x26A7), # Transgender symbol
[all …]
/linux/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A Dgaudi_blocks.h16 #define mmNIC0_PHY0_BASE 0x0ull
17 #define NIC0_PHY0_MAX_OFFSET 0x9F13
18 #define mmMME0_ACC_BASE 0x7FFC020000ull
19 #define MME0_ACC_MAX_OFFSET 0x5C00
20 #define MME0_ACC_SECTION 0x20000
21 #define mmMME0_SBAB_BASE 0x7FFC040000ull
22 #define MME0_SBAB_MAX_OFFSET 0x5800
23 #define MME0_SBAB_SECTION 0x1000
24 #define mmMME0_PRTN_BASE 0x7FFC041000ull
25 #define MME0_PRTN_MAX_OFFSET 0x5000
[all …]
/linux/drivers/gpu/drm/amd/display/dc/mpc/dcn30/
H A Ddcn30_mpc.c44 #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
54 for (opp_id = 0; opp_id < MAX_OPP; opp_id++) { in mpc3_mpc_init()
58 1, MPC_OUT_FLOW_CONTROL_COUNT, 0); in mpc3_mpc_init()
74 1, MPC_OUT_FLOW_CONTROL_COUNT, 0); in mpc3_mpc_init_single_inst()
86 if (status == 0xf) in mpc3_is_dwb_idle()
99 REG_SET(DWB_MUX[dwb_id], 0, in mpc3_set_dwb_mux()
109 REG_SET(DWB_MUX[dwb_id], 0, in mpc3_disable_dwb_mux()
110 MPC_DWB0_MUX, 0xf); in mpc3_disable_dwb_mux()
127 MPC_OUT_RATE_CONTROL, 0); in mpc3_set_out_rate_control()
144 case 0: in mpc3_get_ogam_current()
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos4210.dtsi178 #size-cells = <0>;
194 reg = <0x900>;
213 reg = <0x901>;
230 bus_leftbus_opp_table: opp-table-0 {
249 reg = <0x02020000 0x20000>;
252 ranges = <0 0x02020000 0x20000>;
254 smp-sram@0 {
256 reg = <0x0 0x1000>;
261 reg = <0x1f000 0x1000>;
267 reg = <0x10023ca0 0x20>;
[all …]

123