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/linux/drivers/clk/mediatek/
H A Dclk-mt8186-vdec.c16 .set_ofs = 0x0,
17 .clr_ofs = 0x4,
18 .sta_ofs = 0x0,
22 .set_ofs = 0x190,
23 .clr_ofs = 0x190,
24 .sta_ofs = 0x190,
28 .set_ofs = 0x200,
29 .clr_ofs = 0x204,
30 .sta_ofs = 0x200,
34 .set_ofs = 0x8,
[all …]
/linux/drivers/media/platform/chips-media/coda/
H A Dcoda_regs.h14 #define CODA_REG_BIT_CODE_RUN 0x000
15 #define CODA_REG_RUN_ENABLE (1 << 0)
16 #define CODA_REG_BIT_CODE_DOWN 0x004
17 #define CODA_DOWN_ADDRESS_SET(x) (((x) & 0xffff) << 16)
18 #define CODA_DOWN_DATA_SET(x) ((x) & 0xffff)
19 #define CODA_REG_BIT_HOST_IN_REQ 0x008
20 #define CODA_REG_BIT_INT_CLEAR 0x00c
21 #define CODA_REG_BIT_INT_CLEAR_SET 0x1
22 #define CODA_REG_BIT_INT_STATUS 0x010
23 #define CODA_REG_BIT_CODE_RESET 0x014
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-prt8mm.dts22 reg = <0x0 0x40000000 0 0x40000000>;
28 pinctrl-0 = <&pinctrl_gpio_leds>;
32 gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
64 pinctrl-0 = <&pinctrl_i2c1>;
69 reg = <0x34>;
70 #sound-dai-cells = <0>;
77 pinctrl-0 = <&pinctrl_i2c2>;
82 reg = <0x60>;
83 regulator-name = "0V9_CORE";
94 pinctrl-0 = <&pinctrl_i2c3>;
[all …]
H A Dimx8mm-evk.dts42 pinctrl-0 = <&pinctrl_flexspi>;
45 flash@0 {
46 reg = <0>;
60 pinctrl-0 = <&pinctrl_usdhc3>;
71 MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
72 MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
73 MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
74 MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
75 MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
76 MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
[all …]
H A Dimx8mn-var-som.dtsi20 reg = <0x0 0x40000000 0 0x40000000>;
26 pinctrl-0 = <&pinctrl_reg_eth_phy>;
62 pinctrl-0 = <&pinctrl_ecspi1>;
64 <&gpio1 0 GPIO_ACTIVE_LOW>;
70 touchscreen@0 {
71 reg = <0>;
74 pinctrl-0 = <&pinctrl_restouch>;
98 pinctrl-0 = <&pinctrl_fec1>;
108 #size-cells = <0>;
128 pinctrl-0 = <&pinctrl_i2c1>;
[all …]
H A Dimx8mm-ucm-som.dtsi23 pwms = <&pwm2 0 3000000 0>;
24 brightness-levels = <0 255>;
33 pinctrl-0 = <&pinctrl_gpio_led>;
44 #clock-cells = <0>;
109 pinctrl-0 = <&pinctrl_fec1>;
117 #size-cells = <0>;
119 ethphy0: ethernet-phy@0 {
121 reg = <0>;
129 pinctrl-0 = <&pinctrl_i2c2>;
133 reg = <0x4b>;
[all …]
H A Dimx8mm-icore-mx8mm.dtsi30 pinctrl-0 = <&pinctrl_fec1>;
36 #size-cells = <0>;
50 pinctrl-0 = <&pinctrl_i2c1>;
55 reg = <0x08>;
148 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
149 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
150 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
151 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
152 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
153 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
[all …]
H A Dimx8mp-prt8ml.dts21 #clock-cells = <0>;
28 pinctrl-0 = <&pinctrl_pcie_refclk>;
30 #clock-cells = <0>;
66 pinctrl-0 = <&pinctrl_ecspi2>;
74 switch@0 {
76 reg = <0>;
85 #size-cells = <0>;
114 pinctrl-0 = <&pinctrl_fec>;
116 rx-internal-delay-ps = <0>;
117 tx-internal-delay-ps = <0>;
[all …]
H A Dimx8mm-beacon-som.dtsi17 pinctrl-0 = <&pinctrl_usdhc1_gpio>;
26 reg = <0x0 0x40000000 0 0x80000000>;
68 pinctrl-0 = <&pinctrl_fec1>;
76 #size-cells = <0>;
78 ethphy0: ethernet-phy@0 {
80 reg = <0>;
90 pinctrl-0 = <&pinctrl_flexspi>;
93 flash@0 {
94 reg = <0>;
107 pinctrl-0 = <&pinctrl_i2c1>;
[all …]
H A Dimx8mn-beacon-som.dtsi18 pinctrl-0 = <&pinctrl_usdhc1_gpio>;
27 reg = <0x0 0x40000000 0 0x80000000>;
76 pinctrl-0 = <&pinctrl_fec1>;
86 #size-cells = <0>;
88 ethphy0: ethernet-phy@0 {
90 reg = <0>;
100 pinctrl-0 = <&pinctrl_flexspi>;
103 flash@0 {
104 reg = <0>;
117 pinctrl-0 = <&pinctrl_i2c1>;
[all …]
H A Dimx8mm-kontron-sl.dtsi19 reg = <0x0 0x40000000 0 0x80000000>;
61 pinctrl-0 = <&pinctrl_ecspi1>;
65 flash@0 {
68 reg = <0>;
75 partition@0 {
77 reg = <0x0 0x1e0000>;
82 reg = <0x1e0000 0x10000>;
87 reg = <0x1f0000 0x10000>;
96 pinctrl-0 = <&pinctrl_i2c1>;
101 reg = <0x25>;
[all …]
H A Dimx8mm-nitrogen-r2.dts30 pinctrl-0 = <&pinctrl_reg_wlan_vmmc>;
57 pinctrl-0 = <&pinctrl_sound_wm8960>;
83 pinctrl-0 = <&pinctrl_ecspi2>;
90 pinctrl-0 = <&pinctrl_fec1>;
98 #size-cells = <0>;
110 pinctrl-0 = <&pinctrl_flexspi>;
117 pinctrl-0 = <&pinctrl_i2c1>;
122 reg = <0x8>;
214 pinctrl-0 = <&pinctrl_i2c3>;
219 reg = <0x70>;
[all …]
/linux/drivers/media/dvb-frontends/
H A Dmxl5xx_regs.h13 #define HYDRA_INTR_STATUS_REG 0x80030008
14 #define HYDRA_INTR_MASK_REG 0x8003000C
16 #define HYDRA_CRYSTAL_SETTING 0x3FFFC5F0 /* 0 - 24 MHz & 1 - 27 MHz */
17 #define HYDRA_CRYSTAL_CAP 0x3FFFEDA4 /* 0 - 24 MHz & 1 - 27 MHz */
19 #define HYDRA_CPU_RESET_REG 0x8003003C
20 #define HYDRA_CPU_RESET_DATA 0x00000400
22 #define HYDRA_RESET_TRANSPORT_FIFO_REG 0x80030028
23 #define HYDRA_RESET_TRANSPORT_FIFO_DATA 0x00000000
25 #define HYDRA_RESET_BBAND_REG 0x80030024
26 #define HYDRA_RESET_BBAND_DATA 0x00000000
[all …]
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi4_core.h15 #define HDMI_CORE_SYS_VND_IDL 0x0
16 #define HDMI_CORE_SYS_DEV_IDL 0x8
17 #define HDMI_CORE_SYS_DEV_IDH 0xC
18 #define HDMI_CORE_SYS_DEV_REV 0x10
19 #define HDMI_CORE_SYS_SRST 0x14
20 #define HDMI_CORE_SYS_SYS_CTRL1 0x20
21 #define HDMI_CORE_SYS_SYS_STAT 0x24
22 #define HDMI_CORE_SYS_SYS_CTRL3 0x28
23 #define HDMI_CORE_SYS_DCTL 0x34
24 #define HDMI_CORE_SYS_DE_DLY 0xC8
[all …]
/linux/drivers/gpu/drm/omapdrm/dss/
H A Dhdmi4_core.h15 #define HDMI_CORE_SYS_VND_IDL 0x0
16 #define HDMI_CORE_SYS_DEV_IDL 0x8
17 #define HDMI_CORE_SYS_DEV_IDH 0xC
18 #define HDMI_CORE_SYS_DEV_REV 0x10
19 #define HDMI_CORE_SYS_SRST 0x14
20 #define HDMI_CORE_SYS_SYS_CTRL1 0x20
21 #define HDMI_CORE_SYS_SYS_STAT 0x24
22 #define HDMI_CORE_SYS_SYS_CTRL3 0x28
23 #define HDMI_CORE_SYS_DCTL 0x34
24 #define HDMI_CORE_SYS_DE_DLY 0xC8
[all …]
/linux/Documentation/RCU/
H A Dlockdep-splat.rst30 rcu_scheduler_active = 1, debug_locks = 0
32 #0: (&shost->scan_mutex){+.+.}, at: [<ffffffff8145efca>]
33 scsi_scan_host_selected+0x5a/0x150
35 elevator_exit+0x22/0x60
37 cfq_exit_queue+0x43/0x190
40 Pid: 1552, comm: scsi_scan_6 Not tainted 3.0.0-rc5 #17
42 [<ffffffff810abb9b>] lockdep_rcu_dereference+0xbb/0xc0
43 [<ffffffff812b6139>] __cfq_exit_single_io_context+0xe9/0x120
44 [<ffffffff812b626c>] cfq_exit_queue+0x7c/0x190
45 [<ffffffff812a5046>] elevator_exit+0x36/0x60
[all …]
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-pcs-v6_20.h10 #define QPHY_V6_20_PCS_G12S1_TXDEEMPH_M6DB 0x170
11 #define QPHY_V6_20_PCS_G3S2_PRE_GAIN 0x178
12 #define QPHY_V6_20_PCS_RX_SIGDET_LVL 0x190
13 #define QPHY_V6_20_PCS_COM_ELECIDLE_DLY_SEL 0x1b8
14 #define QPHY_V6_20_PCS_TX_RX_CONFIG1 0x1dc
15 #define QPHY_V6_20_PCS_TX_RX_CONFIG2 0x1e0
16 #define QPHY_V6_20_PCS_EQ_CONFIG4 0x1f8
17 #define QPHY_V6_20_PCS_EQ_CONFIG5 0x1fc
H A Dphy-qcom-qmp-pcs-v7.h10 #define QPHY_V7_PCS_SW_RESET 0x000
11 #define QPHY_V7_PCS_PCS_STATUS1 0x014
12 #define QPHY_V7_PCS_POWER_DOWN_CONTROL 0x040
13 #define QPHY_V7_PCS_START_CONTROL 0x044
14 #define QPHY_V7_PCS_POWER_STATE_CONFIG1 0x090
15 #define QPHY_V7_PCS_LOCK_DETECT_CONFIG1 0x0c4
16 #define QPHY_V7_PCS_LOCK_DETECT_CONFIG2 0x0c8
17 #define QPHY_V7_PCS_LOCK_DETECT_CONFIG3 0x0cc
18 #define QPHY_V7_PCS_LOCK_DETECT_CONFIG6 0x0d8
19 #define QPHY_V7_PCS_REFGEN_REQ_CONFIG1 0x0dc
[all …]
H A Dphy-qcom-qmp-pcs-v6-n4.h10 #define QPHY_V6_N4_PCS_SW_RESET 0x000
11 #define QPHY_V6_N4_PCS_PCS_STATUS1 0x014
12 #define QPHY_V6_N4_PCS_POWER_DOWN_CONTROL 0x040
13 #define QPHY_V6_N4_PCS_START_CONTROL 0x044
14 #define QPHY_V6_N4_PCS_POWER_STATE_CONFIG1 0x090
15 #define QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG1 0x0c4
16 #define QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG2 0x0c8
17 #define QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG3 0x0cc
18 #define QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG6 0x0d8
19 #define QPHY_V6_N4_PCS_REFGEN_REQ_CONFIG1 0x0dc
[all …]
H A Dphy-qcom-qmp-pcs-v8.h10 #define QPHY_V8_PCS_SW_RESET 0x000
11 #define QPHY_V8_PCS_PCS_STATUS1 0x014
12 #define QPHY_V8_PCS_POWER_DOWN_CONTROL 0x040
13 #define QPHY_V8_PCS_START_CONTROL 0x044
14 #define QPHY_V8_PCS_POWER_STATE_CONFIG1 0x090
15 #define QPHY_V8_PCS_LOCK_DETECT_CONFIG1 0x0c4
16 #define QPHY_V8_PCS_LOCK_DETECT_CONFIG2 0x0c8
17 #define QPHY_V8_PCS_LOCK_DETECT_CONFIG3 0x0cc
18 #define QPHY_V8_PCS_LOCK_DETECT_CONFIG6 0x0d8
19 #define QPHY_V8_PCS_REFGEN_REQ_CONFIG1 0x0dc
[all …]
H A Dphy-qcom-qmp-pcs-v5.h10 #define QPHY_V5_PCS_SW_RESET 0x000
11 #define QPHY_V5_PCS_PCS_STATUS1 0x014
12 #define QPHY_V5_PCS_POWER_DOWN_CONTROL 0x040
13 #define QPHY_V5_PCS_START_CONTROL 0x044
14 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG1 0x0c4
15 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG2 0x0c8
16 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG3 0x0cc
17 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG6 0x0d8
18 #define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc
19 #define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170
[all …]
/linux/arch/arm/boot/dts/nxp/vf/
H A Dvf610-pinfunc.h14 #define ALT0 0x0
15 #define ALT1 0x1
16 #define ALT2 0x2
17 #define ALT3 0x3
18 #define ALT4 0x4
19 #define ALT5 0x5
20 #define ALT6 0x6
21 #define ALT7 0x7
24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]
/linux/arch/mips/include/asm/dec/
H A Dioasic_addrs.h21 #define IOASIC_SLOT_SIZE 0x00040000
26 #define IOASIC_SYS_ROM (0*IOASIC_SLOT_SIZE) /* system board ROM */
30 #define IOASIC_SCC0 (4*IOASIC_SLOT_SIZE) /* SCC #0 */
52 #define IO_REG_SCSI_DMA_P 0x00 /* SCSI DMA Pointer */
53 #define IO_REG_SCSI_DMA_BP 0x10 /* SCSI DMA Buffer Pointer */
54 #define IO_REG_LANCE_DMA_P 0x20 /* LANCE DMA Pointer */
55 #define IO_REG_SCC0A_T_DMA_P 0x30 /* SCC0A Transmit DMA Pointer */
56 #define IO_REG_SCC0A_R_DMA_P 0x40 /* SCC0A Receive DMA Pointer */
59 #define IO_REG_SCC1A_T_DMA_P 0x50 /* SCC1A Transmit DMA Pointer */
60 #define IO_REG_SCC1A_R_DMA_P 0x60 /* SCC1A Receive DMA Pointer */
[all …]
/linux/include/dt-bindings/clock/
H A Ddm814.h8 #define DM814_CLKCTRL_OFFSET 0x0
12 #define DM814_USB_OTG_HS_CLKCTRL DM814_CLKCTRL_INDEX(0x58)
15 #define DM814_UART1_CLKCTRL DM814_CLKCTRL_INDEX(0x150)
16 #define DM814_UART2_CLKCTRL DM814_CLKCTRL_INDEX(0x154)
17 #define DM814_UART3_CLKCTRL DM814_CLKCTRL_INDEX(0x158)
18 #define DM814_GPIO1_CLKCTRL DM814_CLKCTRL_INDEX(0x15c)
19 #define DM814_GPIO2_CLKCTRL DM814_CLKCTRL_INDEX(0x160)
20 #define DM814_I2C1_CLKCTRL DM814_CLKCTRL_INDEX(0x164)
21 #define DM814_I2C2_CLKCTRL DM814_CLKCTRL_INDEX(0x168)
22 #define DM814_WD_TIMER_CLKCTRL DM814_CLKCTRL_INDEX(0x18c)
[all …]
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dmicrochip,lan966x-oic.yaml48 reg = <0xe00c0120 0x190>;
51 interrupts = <0>;

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