1*17972a5fSHerve Codina# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*17972a5fSHerve Codina%YAML 1.2 3*17972a5fSHerve Codina--- 4*17972a5fSHerve Codina$id: http://devicetree.org/schemas/interrupt-controller/microchip,lan966x-oic.yaml# 5*17972a5fSHerve Codina$schema: http://devicetree.org/meta-schemas/core.yaml# 6*17972a5fSHerve Codina 7*17972a5fSHerve Codinatitle: Microchip LAN966x outband interrupt controller 8*17972a5fSHerve Codina 9*17972a5fSHerve Codinamaintainers: 10*17972a5fSHerve Codina - Herve Codina <herve.codina@bootlin.com> 11*17972a5fSHerve Codina 12*17972a5fSHerve CodinaallOf: 13*17972a5fSHerve Codina - $ref: /schemas/interrupt-controller.yaml# 14*17972a5fSHerve Codina 15*17972a5fSHerve Codinadescription: | 16*17972a5fSHerve Codina The Microchip LAN966x outband interrupt controller (OIC) maps the internal 17*17972a5fSHerve Codina interrupt sources of the LAN966x device to an external interrupt. 18*17972a5fSHerve Codina When the LAN966x device is used as a PCI device, the external interrupt is 19*17972a5fSHerve Codina routed to the PCI interrupt. 20*17972a5fSHerve Codina 21*17972a5fSHerve Codinaproperties: 22*17972a5fSHerve Codina compatible: 23*17972a5fSHerve Codina const: microchip,lan966x-oic 24*17972a5fSHerve Codina 25*17972a5fSHerve Codina '#interrupt-cells': 26*17972a5fSHerve Codina const: 2 27*17972a5fSHerve Codina 28*17972a5fSHerve Codina interrupt-controller: true 29*17972a5fSHerve Codina 30*17972a5fSHerve Codina reg: 31*17972a5fSHerve Codina maxItems: 1 32*17972a5fSHerve Codina 33*17972a5fSHerve Codina interrupts: 34*17972a5fSHerve Codina maxItems: 1 35*17972a5fSHerve Codina 36*17972a5fSHerve Codinarequired: 37*17972a5fSHerve Codina - compatible 38*17972a5fSHerve Codina - '#interrupt-cells' 39*17972a5fSHerve Codina - interrupt-controller 40*17972a5fSHerve Codina - interrupts 41*17972a5fSHerve Codina - reg 42*17972a5fSHerve Codina 43*17972a5fSHerve CodinaadditionalProperties: false 44*17972a5fSHerve Codina 45*17972a5fSHerve Codinaexamples: 46*17972a5fSHerve Codina - | 47*17972a5fSHerve Codina interrupt-controller@e00c0120 { 48*17972a5fSHerve Codina compatible = "microchip,lan966x-oic"; 49*17972a5fSHerve Codina reg = <0xe00c0120 0x190>; 50*17972a5fSHerve Codina #interrupt-cells = <2>; 51*17972a5fSHerve Codina interrupt-controller; 52*17972a5fSHerve Codina interrupts = <0>; 53*17972a5fSHerve Codina interrupt-parent = <&intc>; 54*17972a5fSHerve Codina }; 55*17972a5fSHerve Codina... 56