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Searched +full:0 +full:x18013000 (Results 1 – 7 of 7) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dbrcm,iproc-pcie.yaml117 reg = <0x18012000 0x1000>;
120 interrupt-map-mask = <0 0 0 0>;
121 interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
123 linux,pci-domain = <0>;
125 bus-range = <0x00 0xff>;
130 ranges = <0x81000000 0 0 0x28000000 0 0x00010000>,
131 <0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
133 phys = <&phy 0 5>;
137 brcm,pcie-ob-axi-offset = <0x00000000>;
155 reg = <0x18013000 0x1000>;
[all …]
H A Dbrcm,iproc-pcie.txt77 reg = <0x18012000 0x1000>;
80 interrupt-map-mask = <0 0 0 0>;
81 interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
83 linux,pci-domain = <0>;
85 bus-range = <0x00 0xff>;
90 ranges = <0x81000000 0 0 0x28000000 0 0x00010000
91 0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
93 phys = <&phy 0 5>;
97 brcm,pcie-ob-axi-offset = <0x00000000>;
115 reg = <0x18013000 0x1000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm-hr2.dtsi45 #size-cells = <0>;
47 cpu0: cpu@0 {
51 reg = <0x0>;
64 ranges = <0x00000000 0x19000000 0x00023000>;
68 a9pll: arm_clk@0 {
69 #clock-cells = <0>;
72 reg = <0x0 0x100
[all...]
H A Dbcm-cygnus.dtsi48 memory@0 {
50 reg = <0 0>;
55 #size-cells = <0>;
57 cpu@0 {
61 reg = <0x0>;
74 ranges = <0x00000000 0x19000000 0x1000000>;
80 reg = <0x2020
[all...]
H A Dbcm-nsp.dtsi54 #size-cells = <0>;
56 cpu0: cpu@0 {
60 reg = <0x0>;
68 secondary-boot-reg = <0xffff0fec>;
69 reg = <0x1>;
82 ranges = <0x00000000 0x19000000 0x00023000>;
86 a9pll: arm_clk@0 {
87 #clock-cells = <0>;
[all...]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7996/
H A Dregs.h84 #define MT_RRO_TOP_BASE 0xA000
87 #define MT_RRO_BA_BITMAP_BASE0 MT_RRO_TOP(0x8)
88 #define MT_RRO_BA_BITMAP_BASE1 MT_RRO_TOP(0xC)
89 #define WF_RRO_AXI_MST_CFG MT_RRO_TOP(0xB8)
91 #define MT_RRO_ADDR_ARRAY_BASE1 MT_RRO_TOP(0x34)
94 #define MT_RRO_IND_CMD_SIGNATURE_BASE0 MT_RRO_TOP(0x38)
95 #define MT_RRO_IND_CMD_SIGNATURE_BASE1 MT_RRO_TOP(0x3C)
96 #define MT_RRO_IND_CMD_0_CTRL0 MT_RRO_TOP(0x40)
99 #define MT_RRO_PARTICULAR_CFG0 MT_RRO_TOP(0x5C)
100 #define MT_RRO_PARTICULAR_CFG1 MT_RRO_TOP(0x60)
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7915/
H A Dregs.h130 #define MT_MCU_WFDMA0_BASE 0x2000
133 #define MT_MCU_WFDMA0_DUMMY_CR MT_MCU_WFDMA0(0x120)
136 #define MT_MCU_WFDMA1_BASE 0x3000
140 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
146 #define MT_PLE_BASE 0x820c0000
149 #define MT_PLE_HOST_RPT0 MT_PLE(0x030)
154 #define MT_FL_Q2_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0x8)
155 #define MT_FL_Q3_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0xc)
165 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))
167 #define MT_PSE_BASE 0x820c8000
[all …]