Lines Matching +full:0 +full:x18013000

48 	memory@0 {
50 		reg = <0 0>;
55 		#size-cells = <0>;
57 		cpu@0 {
61 			reg = <0x0>;
74 		ranges = <0x00000000 0x19000000 0x1000000>;
80 			reg = <0x20200 0x100>;
88 			#address-cells = <0>;
90 			reg = <0x21000 0x1000>,
91 			      <0x20100 0x100>;
96 			reg = <0x22000 0x1000>;
110 			reg = <0x0301c800 0x2c>;
117 			reg = <0x0301d0a0 0x14>;
119 			#size-cells = <0>;
121 			pcie0_phy: pcie-phy@0 {
122 				reg = <0>;
123 				#phy-cells = <0>;
128 				#phy-cells = <0>;
134 			reg = <0x0301d0c8 0x30>,
135 			      <0x0301d24c 0x2c>;
155 			reg = <0x03024024 0x40>;
164 			reg = <0x03024800 0x50>,
165 			      <0x03024008 0x18>;
172 			interrupts = <0>;
177 			reg = <0x18002000 0x8>;
178 			#size-cells = <0>;
182 			gphy0: ethernet-phy@0 {
183 				reg = <0>;
193 			reg = <0x18007000 0x1000>;
198 				#size-cells = <0>;
200 				port@0 {
201 					reg = <0>;
226 			reg = <0x18008000 0x100>;
228 			#size-cells = <0>;
236 			reg = <0x18009000 0x1000>;
244 			reg = <0x1800a000 0x50>,
245 			      <0x0301d164 0x20>;
256 			reg = <0x1800b000 0x100>;
258 			#size-cells = <0>;
266 			reg = <0x18012000 0x1000>;
269 			interrupt-map-mask = <0 0 0 0>;
270 			interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
272 			linux,pci-domain = <0>;
274 			bus-range = <0x00 0xff>;
279 			ranges = <0x81000000 0 0	  0x28000000 0 0x00010000>,
280 				 <0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
301 			reg = <0x18013000 0x1000>;
304 			interrupt-map-mask = <0 0 0 0>;
305 			interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
309 			bus-range = <0x00 0xff>;
314 			ranges = <0x81000000 0 0	  0x48000000 0 0x00010000>,
315 				 <0x82000000 0 0x40000000 0x40000000 0 0x04000000>;
336 			reg = <0x18018000 0x1000>;
353 			reg = <0x18020000 0x100>;
364 			reg = <0x18021000 0x100>;
375 			reg = <0x18022000 0x100>;
386 			reg = <0x18023000 0x100>;
397 			reg = <0x18028000 0x1000>;
399 			#size-cells = <0>;
401 			pinctrl-0 = <&spi_0>;
409 			reg = <0x18029000 0x1000>;
411 			#size-cells = <0>;
413 			pinctrl-0 = <&spi_1>;
421 			reg = <0x1802a000 0x1000>;
423 			#size-cells = <0>;
425 			pinctrl-0 = <&spi_2>;
433 			reg = <0x18032000 0x28>;
438 			reg = <0x18041000 0x100>;
448 			reg = <0x18042000 0x1000>,
449 			      <0x18110000 0x1000>;
457 			reg = <0x18043000 0x100>;
467 			reg = <0x18046000 0x600>, <0xf8105408 0x600>,
468 			      <0x18046f00 0x20>;
473 			#size-cells = <0>;
480 			reg = <0x18048000 0x100>;
487 			reg = <0x18048800 0x100>;
494 			reg = <0x180a0000 0x1000>;
504 			reg = <0x180a2000 0x1000>;
517 			reg = <0x180a5000 0x668>;
525 			gpio-ranges = <&pinctrl 0 42 1>,
580 			reg = <0x180a6000 0xc30>;
606 			reg = <0x180aa500 0xc4>;
614 			reg = <0x180ac000 0x14c>;
620 			col-debounce-filter-period = <0>;
621 			status-debounce-filter-period = <0>;