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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ull-jozacp.dts25 led-0 {
28 function-enumerator = <0>;
29 pwms = <&pwm1 0 10000000 0>;
37 pwms = <&pwm3 0 10000000 0>;
45 pwms = <&pwm5 0 10000000 0>;
59 pwms = <&pwm2 0 10000000 0>;
67 pwms = <&pwm4 0 10000000 0>;
75 pwms = <&pwm6 0 10000000 0>;
98 pinctrl-0 = <&pinctrl_vbus>;
110 pinctrl-0 = <&pinctrl_wifi_npd>;
[all …]
H A Dimx6sl-tolino-vision.dts29 pwms = <&ec 0 50000>;
36 pinctrl-0 = <&pinctrl_backlight_power>;
49 pinctrl-0 = <&pinctrl_gpio_keys>;
77 pinctrl-0 = <&pinctrl_leds>;
79 led-0 {
97 reg = <0x80000000 0x20000000>;
103 pinctrl-0 = <&pinctrl_wifi_power>;
114 pinctrl-0 = <&pinctrl_wifi_reset>;
116 reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
122 pinctrl-0 = <&pinctrl_i2c1>;
[all …]
/linux/arch/m68k/include/asm/
H A Dapollohw.h52 #define IO_BASE 0x80000000
62 #define SAU7_SIO01_PHYSADDR 0x10400
63 #define SAU7_SIO23_PHYSADDR 0x10500
64 #define SAU7_RTC_PHYSADDR 0x10900
65 #define SAU7_PICA 0x11000
66 #define SAU7_PICB 0x11100
67 #define SAU7_CPUCTRL 0x10100
68 #define SAU7_TIMER 0x010800
70 #define SAU8_SIO01_PHYSADDR 0x8400
71 #define SAU8_RTC_PHYSADDR 0x8900
[all …]
/linux/arch/arc/boot/dts/
H A Dvdk_axs10x_mb.dtsi13 ranges = <0x00000000 0xe0000000 0x10000000>;
20 #clock-cells = <0>;
26 #clock-cells = <0>;
30 #clock-cells = <0>;
39 reg = < 0x18000 0x2000 >;
43 snps,phy-addr = < 0 >; // VDK model phy address is 0
51 reg = < 0x40000 0x100 >;
57 reg = <0x20000 0x100>;
67 reg = <0x21000 0x100>;
77 reg = <0x22000 0x100>;
[all …]
H A Daxs10x_mb.dtsi17 ranges = <0x00000000 0x0 0xe0000000 0x10000000>;
23 reg = <0x11220 0x4>;
28 reg = <0x100a0 0x10>;
30 #clock-cells = <0>;
37 #clock-cells = <0>;
43 #clock-cells = <0>;
49 #clock-cells = <0>;
62 #clock-cells = <0>;
68 reg = <0x10080 0x10>, <0x110 0x10>;
69 #clock-cells = <0>;
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnvidia,tegra234-pinmux.yaml126 reg = <0x2430000 0x17000>;
129 pinctrl-0 = <&pex_rst_c5_out_state>;
H A Dnvidia,tegra194-pinmux.yaml266 reg = <0x2430000 0x17000>;
269 pinctrl-0 = <&pex_rst_c5_out_state>;
/linux/drivers/media/pci/intel/ipu6/
H A Dipu6-platform-isys-csi2-reg.h9 #define CSI_REG_BASE 0x220000
10 #define CSI_REG_PORT_BASE(id) (CSI_REG_BASE + (id) * 0x1000)
13 #define CSI_REG_PORT_GPREG_SRST 0x0
14 #define CSI_REG_PORT_GPREG_CSI2_SLV_REG_SRST 0x4
15 #define CSI_REG_PORT_GPREG_CSI2_PORT_CONTROL 0x8
24 #define CSI_PORT_REG_BASE_IRQ_CSI 0x80
25 #define CSI_PORT_REG_BASE_IRQ_CSI_SYNC 0xA0
26 #define CSI_PORT_REG_BASE_IRQ_S2M_SIDS0TOS7 0xC0
27 #define CSI_PORT_REG_BASE_IRQ_S2M_SIDS8TOS15 0xE0
29 #define CSI_PORT_REG_BASE_IRQ_EDGE_OFFSET 0x0
[all …]
/linux/arch/arm/mach-imx/
H A Dmx2x.h16 #define MX2x_AIPI_BASE_ADDR 0x10000000
18 #define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000)
19 #define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000)
20 #define MX2x_GPT1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x03000)
21 #define MX2x_GPT2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x04000)
22 #define MX2x_GPT3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x05000)
23 #define MX2x_PWM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x06000)
24 #define MX2x_RTC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x07000)
25 #define MX2x_KPP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x08000)
26 #define MX2x_OWIRE_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x09000)
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dinterlaken-lac-portals.dtsi34 #address-cells = <0x1>;
35 #size-cells = <0x1>;
38 lportal0: lac-portal@0 {
39 compatible = "fsl,interlaken-lac-portal-v1.0";
40 reg = <0x0 0x1000>;
44 compatible = "fsl,interlaken-lac-portal-v1.0";
45 reg = <0x1000 0x1000>;
49 compatible = "fsl,interlaken-lac-portal-v1.0";
50 reg = <0x2000 0x1000>;
54 compatible = "fsl,interlaken-lac-portal-v1.0";
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Ddra74x.dtsi49 reg = <0x41500000 0x100>;
55 reg = <0x41501000 0x4>,
56 <0x41501010 0x4>,
57 <0x41501014 0x4>;
65 clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
69 ranges = <0x0 0x41501000 0x1000>;
73 mmu0_dsp2: mmu@0 {
75 reg = <0x0 0x100>;
77 #iommu-cells = <0>;
78 ti,syscon-mmuconfig = <&dsp2_system 0x0>;
[all …]
/linux/drivers/soc/tegra/cbb/
H A Dtegra234-cbb.c8 * Error types supported by CBB2.0 are:
27 #define FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0 0x0
28 #define FABRIC_EN_CFG_STATUS_0_0 0x40
29 #define FABRIC_EN_CFG_ADDR_INDEX_0_0 0x60
30 #define FABRIC_EN_CFG_ADDR_LOW_0 0x80
31 #define FABRIC_EN_CFG_ADDR_HI_0 0x84
33 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_INDEX_0_0 0x100
34 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_LOW_0 0x140
35 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_HI_0 0x144
37 #define FABRIC_MN_INITIATOR_ERR_EN_0 0x200
[all …]
/linux/sound/pci/au88x0/
H A Dau8830.h18 #define NR_ADB 0x20
19 #define NR_SRC 0x10
20 #define NR_A3D 0x10
21 #define NR_MIXIN 0x20
22 #define NR_MIXOUT 0x10
23 #define NR_WT 0x40
26 #define VORTEX_ADBDMA_STAT 0x27e00 /* read only, subbuffer, DMA pos */
27 #define POS_MASK 0x00000fff
28 #define POS_SHIFT 0x0
29 #define ADB_SUBBUF_MASK 0x00003000 /* ADB only. */
[all …]
/linux/arch/arm64/boot/dts/marvell/mmp/
H A Dpxa1908.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
21 reg = <0 0>;
28 reg = <0 1>;
35 reg = <0 2>;
42 reg = <0 3>;
77 reg = <0 0xc0010000 0 0x10000>;
87 reg = <0 0xd1df9000 0 0x1000>,
88 <0 0xd1dfa000 0 0x2000>,
90 <0 0xd1dfc000 0 0x2000>,
[all …]
/linux/arch/x86/platform/ce4100/
H A Dfalconfalls.dts16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
26 soc@0 {
36 reg = <0xfec00000 0x1000>;
41 reg = <0xfed00000 0x200>;
46 reg = <0xfee00000 0x1000>;
54 bus-range = <0 0>;
55 ranges = <0x2000000 0 0xbffff000 0xbffff000 0 0x1000
56 0x2000000 0 0xdffe0000 0xdffe0000 0 0x1000
[all …]
/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dinterlaken-lac.txt31 There is a full register set at 0x0000-0x0FFF (also known as the "hypervisor"
32 version), and a subset at 0x1000-0x1FFF. The former is a superset of the
45 IP Block Revision Register (IPBRR0) at offset 0x0BF8.
51 0x02000100 T4240
78 reg = <0x229000 0x1000>;
84 reg = <0x228000 0x1000>;
136 Register (IPBRR0), at offset 0x0BF8, and Y is the Minor version
161 #address-cells = <0x1>;
162 #size-cells = <0x1>;
164 ranges = <0x0 0xf 0xf4400000 0x20000>;
[all …]
/linux/drivers/net/wireless/ath/ath10k/
H A Dcoredump.c21 {0x800, 0x810},
22 {0x820, 0x82C},
23 {0x830, 0x8F4},
24 {0x90C, 0x91C},
25 {0xA14, 0xA18},
26 {0xA84, 0xA94},
27 {0xAA8, 0xAD4},
28 {0xADC, 0xB40},
29 {0x1000, 0x10A4},
30 {0x10BC, 0x111C},
[all …]
/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2m.dtsi27 ranges = <0x40000000 0x40000000 0x10000000>,
28 <0x10000000 0x10000000 0x00020000>;
31 interrupt-map-mask = <0 63>;
32 interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
33 <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
34 <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
35 <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
36 <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
37 <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
38 <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drvu_reg.h12 #define RVU_AF_MSIXTR_BASE (0x10)
13 #define RVU_AF_ECO (0x20)
14 #define RVU_AF_BLK_RST (0x30)
15 #define RVU_AF_PF_BAR4_ADDR (0x40)
16 #define RVU_AF_RAS (0x100)
17 #define RVU_AF_RAS_W1S (0x108)
18 #define RVU_AF_RAS_ENA_W1S (0x110)
19 #define RVU_AF_RAS_ENA_W1C (0x118)
20 #define RVU_AF_GEN_INT (0x120)
21 #define RVU_AF_GEN_INT_W1S (0x128)
[all …]
/linux/drivers/tty/vt/
H A Ducs_width_table.h_shipped7 * Unicode Version: 16.0.0
12 { 0x00AD, 0x00AD }, /* SOFT HYPHEN */
13 { 0x0300, 0x036F }, /* COMBINING GRAVE ACCENT - COMBINING LATIN SMALL LETTER X */
14 { 0x0483, 0x0489 }, /* COMBINING CYRILLIC TITLO - COMBINING CYRILLIC MILLIONS SIGN */
15 { 0x0591, 0x05BD }, /* HEBREW ACCENT ETNAHTA - HEBREW POINT METEG */
16 { 0x05BF, 0x05BF }, /* HEBREW POINT RAFE */
17 { 0x05C1, 0x05C2 }, /* HEBREW POINT SHIN DOT - HEBREW POINT SIN DOT */
18 { 0x05C4, 0x05C5 }, /* HEBREW MARK UPPER DOT - HEBREW MARK LOWER DOT */
19 { 0x05C7, 0x05C7 }, /* HEBREW POINT QAMATS QATAN */
20 { 0x0600, 0x0605 }, /* ARABIC NUMBER SIGN - ARABIC NUMBER MARK ABOVE */
[all …]
/linux/drivers/clk/qcom/
H A Dgcc-sdx65.c36 .offset = 0x0,
39 .enable_reg = 0x6d000,
40 .enable_mask = BIT(0),
53 { 0x1, 2 },
58 .offset = 0x0,
73 { P_BI_TCXO, 0 },
91 { P_BI_TCXO, 0 },
105 { P_BI_TCXO, 0 },
119 { P_PCIE_PIPE_CLK, 0 },
129 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
[all …]
/linux/drivers/net/ethernet/wangxun/libwx/
H A Dwx_type.h16 #define WX_NCSI_SUP 0x8000
17 #define WX_NCSI_MASK 0x8000
18 #define WX_WOL_SUP 0x4000
19 #define WX_WOL_MASK 0x4000
22 #define WX_PCIE_MSIX_TBL_SZ_MASK 0x7FF
23 #define WX_PCI_LINK_STATUS 0xB2
29 #define WX_VF_IND_SHIFT(_v) FIELD_GET(GENMASK(4, 0), (_v))
32 #define WX_MIS_PWR 0x10000
33 #define WX_MIS_RST 0x1000C
35 #define WX_MIS_RST_SW_RST BIT(0)
[all …]
/linux/drivers/interconnect/qcom/
H A Dsm8650.c29 .port_offsets = { 0xc000 },
31 .urg_fwd = 0,
32 .prio_fwd_disable = 0,
47 .port_offsets = { 0xd000 },
49 .urg_fwd = 0,
50 .prio_fwd_disable = 0,
74 .port_offsets = { 0xe000 },
76 .urg_fwd = 0,
77 .prio_fwd_disable = 0,
92 .port_offsets = { 0xf000 },
[all …]
H A Dmilos.c142 .port_offsets = { 0xc000 },
144 .urg_fwd = 0,
159 .port_offsets = { 0xf200 },
161 .urg_fwd = 0,
176 .port_offsets = { 0x10000 },
178 .urg_fwd = 0,
193 .port_offsets = { 0x14000 },
195 .urg_fwd = 0,
210 .port_offsets = { 0x12000 },
212 .urg_fwd = 0,
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8976.dtsi27 #clock-cells = <0>;
33 #size-cells = <0>;
35 cpu0: cpu@0 {
38 reg = <0x0>;
49 reg = <0x1>;
60 reg = <0x2>;
71 reg = <0x3>;
82 reg = <0x100>;
93 reg = <0x101>;
104 reg = <0x102>;
[all …]

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