Lines Matching +full:0 +full:x17000
49 reg = <0x41500000 0x100>;
55 reg = <0x41501000 0x4>,
56 <0x41501010 0x4>,
57 <0x41501014 0x4>;
65 clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
69 ranges = <0x0 0x41501000 0x1000>;
73 mmu0_dsp2: mmu@0 {
75 reg = <0x0 0x100>;
77 #iommu-cells = <0>;
78 ti,syscon-mmuconfig = <&dsp2_system 0x0>;
84 reg = <0x41502000 0x4>,
85 <0x41502010 0x4>,
86 <0x41502014 0x4>;
95 clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
99 ranges = <0x0 0x41502000 0x1000>;
103 mmu1_dsp2: mmu@0 {
105 reg = <0x0 0x100>;
107 #iommu-cells = <0>;
108 ti,syscon-mmuconfig = <&dsp2_system 0x1>;
114 reg = <0x41000000 0x48000>,
115 <0x41600000 0x8000>,
116 <0x41700000 0x8000>;
118 ti,bootreg = <&scm_conf 0x560 10>;
121 resets = <&prm_dsp2 0>;
122 clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
133 reg = <0 0x80>,
134 <0x4054 0x4>,
135 <0x4300 0x20>,
136 <0x9054 0x4>,
137 <0x9300 0x20>;
186 segment@0 {
187 usb4_tm: target-module@140000 { /* 0x48940000, ap 75 3c.0 */
189 reg = <0x140000 0x4>,
190 <0x140010 0x4>;
202 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>;
206 ranges = <0x0 0x140000 0x20000>;
208 omap_dwc3_4: omap_dwc3_4@0 {
210 reg = <0 0x10000>;
219 reg = <0x10000 0x17000>;